[OpenBIOS] Sun OBP bugs in 1.0RC1

[Peter]

This deviation is the documented fix for one of the SunOS crashes.
Sun4m requires there to be 4 CPU-specific interrupts and counters
(regardless of the number of CPUs) before the system-wide interrupt
and counter.  The OBP registers you point out were broken in this
regard:  it only mapped a single CPU specific interrupt and counter.
This allowed OBP to boot, say, linux, but not SunOS.

On 3/10/07, Blue Swirl <blueswir1 at hotmail.com> wrote:
> >Here's a patch file based on the latest snapshot that addresses
> >everything up through #9, excluding #5 (which requires a tweak to
> >qemu).  It includes the patch for #2 written by Blue Swirl, which
> >copies the entire contents of the ROM into RAM.
>
> Thank you for your work, it would be great to get more OSes running on
> Qemu/OpenBIOS.
>
> Just one comment: On my Sun4m machine (SS-5) the OBP properties for
> interrupt and counter reg nodes are as follows:
>
> $ cat obio/interrupt\@0\,e00000/reg
> 00000000.00e00000.00000010.00000000.00e10000.00000010
> $ cat obio/counter\@0\,d00000/reg
> 00000000.00d00000.00000010.00000000.00d10000.00000010
>
> Your patch deviates from this. If you want to emulate a SS-10, it may be
> better to add it as a new sub-machine type to Qemu and OpenBIOS. I don't
> know how much SS-5 and SS-10 differ. For example, what is the MMU on SS-10,
> is it also Swift (SRMMU)?
>
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