[openfirmware] r1462 - cpu/x86/pc/olpc/via dev/via/unichrome
svn at openfirmware.info
svn at openfirmware.info
Sat Nov 7 10:28:16 CET 2009
Author: wmb
Date: 2009-11-07 09:28:16 +0000 (Sat, 07 Nov 2009)
New Revision: 1462
Modified:
cpu/x86/pc/olpc/via/dramtiming.fth
dev/via/unichrome/unichrome.fth
Log:
OLPC trac 9333 - fixed screen flicker by setting the VIA display FIFO registers.
Modified: cpu/x86/pc/olpc/via/dramtiming.fth
===================================================================
--- cpu/x86/pc/olpc/via/dramtiming.fth 2009-11-06 07:36:09 UTC (rev 1461)
+++ cpu/x86/pc/olpc/via/dramtiming.fth 2009-11-07 09:28:16 UTC (rev 1462)
@@ -87,8 +87,7 @@
rank-size #ranks * constant total-size
[then]
-\ h# 400.0000 constant /fbmem
-h# 1000.0000 constant /fbmem
+h# 400.0000 constant /fbmem
: >fbmem-base ( size/64M -- low high )
d# 26 lshift ( memsize-in-bytes )
/fbmem - ( memsize-less-framebuf-size )
Modified: dev/via/unichrome/unichrome.fth
===================================================================
--- dev/via/unichrome/unichrome.fth 2009-11-06 07:36:09 UTC (rev 1461)
+++ dev/via/unichrome/unichrome.fth 2009-11-07 09:28:16 UTC (rev 1462)
@@ -732,7 +732,7 @@
80 17 crt-clr \ Assert reset - Turn off screen
set-secondary-timings
random-stuff
- lower-power
+ mode-independent-init
\ Turn on power here?
1e 6c crt-clr \ 10=>0: VCK source is VCK PLL 0e=>0: LCDCK PLL RefClk from X1 Pin
pll set-lcdck
@@ -768,12 +768,15 @@
\ 00 08 h# 6b crt-mask \ Not simultaneous mode
40 16 seq-set \ manual says the bit is reserved, but the viafb driver says "CRT path set to IGA2"
+ 80 59 seq-clr \ Turn off IGA1 in power control register
;
: olpc-crt-off ( -- )
+ 80 59 seq-clr \ Turn off IGA1 in power control register
30 1b seq-clr \ IGA1 engine clock off
30 36 crt-set \ DAC off
;
: olpc-crt-on ( -- )
+ 80 59 seq-set \ Turn on IGA1 in power control register
30 1b seq-set \ IGA1 engine clock on
30 36 crt-clr \ DAC on
;
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