[OpenBIOS] r351 - cpu/x86/pc/olpc
svn at openbios.org
svn at openbios.org
Fri May 4 09:00:17 CEST 2007
Author: wmb
Date: 2007-05-04 09:00:17 +0200 (Fri, 04 May 2007)
New Revision: 351
Modified:
cpu/x86/pc/olpc/chipinit.fth
cpu/x86/pc/olpc/romreset.bth
cpu/x86/pc/olpc/vsapci.fth
Log:
OLPC - (a) Changed frame buffer size to 16M (b) fixed some MSR and PCI
header values based on a comparison with LinuxBIOS for LX.
Modified: cpu/x86/pc/olpc/chipinit.fth
===================================================================
--- cpu/x86/pc/olpc/chipinit.fth 2007-05-04 06:56:57 UTC (rev 350)
+++ cpu/x86/pc/olpc/chipinit.fth 2007-05-04 07:00:17 UTC (rev 351)
@@ -339,7 +339,11 @@
msr: 0000.1210 00000000.00000003. \ Suspend on halt and pause
msr: 0000.1900 00000000.02001131. \ Pausedly 16 clocks, SUSP + TSC_SUSP
msr: 0000.1920 00000000.0000000f. \ Enable L2 cache
- msr: 0000.1a00 00000000.00000001. \ GX p 178 Imprecise exceptions
+ msr: 0000.1930 00000000.00070303. \ MSR_PMODE
+ msr: 0000.1981 00000000.2814d352. \ MSS_ARRAY_CTL0 - cache timings - value from PRS
+ msr: 0000.1982 00000000.1068334d. \ MSS_ARRAY_CTL1 - cache timings - value from PRS
+ msr: 0000.1983 00000106.83104104. \ MSS_ARRAY_CTL2 - cache timings - value from PRS
+ msr: 0000.1a00 00000000.00000001. \ Imprecise exceptions
\ northbridgeinit: GLIUS
\ msr: 1000.0020 20000000.000fff80. \ 0 - 7.ffff low RAM Early startup
@@ -351,13 +355,13 @@
\ msr: 1000.0026 000000ff.fff00000. \ Unmapped - default
\ Graphics
-\ msr: 1000.0029 20a7e0fd.7fffd000. \ fd00.0000 - fd7f.ffff mapped to 77e.0000 Memsize dependent (Frame Buffer)
+\ msr: 1000.0029 20a7e0fd.ffffd000. \ fd00.0000 - fdff.ffff mapped to f00.0000 Memsize dependent, fbsize dependent
msr: 1000.002a 801ffcfe.007fe004. \ fe00.4000 - fe00.7fff mapped to 0 in DC space
\ msr: 1000.002b 00000000.000fffff. \ Unmapped - default
\ msr: 1000.002c 00000000.00000000. \ Unmapped - default (Swiss Cheese)
- msr: 1000.0080 00000000.00000003. \ Coherency
+ msr: 1000.0080 00000000.00000003. \ Coherency - route snoops to CPU
msr: 1000.0082 80000000.00000000. \ Arbitration
msr: 1000.0083 00000000.0000ff00. \ Disable SMIs
msr: 1000.0084 00000000.0000ff00. \ Disable Async errors
@@ -376,11 +380,11 @@
\ msr: 4000.0023 000000ff.fff00000. \ Unmapped - default
msr: 4000.0024 200000fe.004ffffc. \ fe00.4000 - fe00.7fff DC, route to GLIU0
msr: 4000.0025 400000fe.008ffffc. \ fe00.8000 - fe00.bfff VP, route to VP in GLIU1
- msr: 4000.0026 a00000fe.00cffffc. \ fe00.c000 - fe00.ffff VIP, route to VP in GLIU1
+ msr: 4000.0026 a00000fe.00cffffc. \ fe00.c000 - fe00.ffff VIP, route to VIP in GLIU1
\ msr: 4000.0027 000000ff.fff00000. \ Unmapped - default
\ msr: 4000.0028 000000ff.fff00000. \ Unmapped - default
\ msr: 4000.0029 000000ff.fff00000. \ Unmapped - default
- msr: 4000.002a 200000fd.7fffd000. \ frame buffer - fd00.0000 .. fd7f.ffff, route to GLIU0
+ msr: 4000.002a 200000fd.ffffd000. \ frame buffer - fd00.0000 .. fdff.ffff, route to GLIU0, fbsize
msr: 4000.002b c00000fe.013fe010. \ Security Block - fe01.0000 .. fe01.3fff
\ msr: 4000.002c 20000007.7ff00100. \ 10.0000 - 0f7f.ffff High RAM - Memsize dependent
\ msr: 4000.002d 00000000.000fffff. \ Unmapped - default
@@ -402,7 +406,7 @@
msr: 0000.2001 00000000.00000220.
msr: 4c00.2001 00000000.00000001.
msr: 5000.2001 00000000.00000027.
- msr: 5800.2001 00000000.00000000.
+ msr: 5800.2001 00000000.00000013.
msr: 8000.2001 00000000.00000320.
msr: 0000.1700 00000000.00000400. \ Evict clean lines - necessary for L2
@@ -418,8 +422,8 @@
msr: 0000.180d 00000000.00000000. \ Cache e0000-fffff
\ msr: 0000.180e 00000001.00000001. \ SMM off - default
\ msr: 0000.180f 00000001.00000001. \ DMM off - default
- msr: 0000.1810 fd7ff000.fd000111. \ Video (write through)
- msr: 0000.1811 fe00f000.fe000101. \ GP + DC + VP + VIP registers non-cacheable
+ msr: 0000.1810 fdfff000.fd000111. \ Video (write through), fbsize
+ msr: 0000.1811 fe013000.fe000101. \ GP + DC + VP + VIP + AES registers non-cacheable
\ msr: 0000.1812 00000000.00000000. \ Disabled - default
\ msr: 0000.1813 00000000.00000000. \ Disabled - default
\ msr: 0000.1814 00000000.00000000. \ Disabled - default
@@ -428,32 +432,38 @@
\ msr: 0000.1817 00000000.00000000. \ Disabled - default
\ PCI
-\ msr: 5000.2000 00000000.00105001. \ RO
+\ msr: 5000.2000 00000000.00105400. \ RO
msr: 5000.2001 00000000.00000017. \ Priority 1, domain 7
msr: 5000.2002 00000000.003f003f. \ No SMIs
msr: 5000.2003 00000000.00370037. \ No ERRs
msr: 5000.2004 00000000.00000015. \ Clock gating for 3 clocks
msr: 5000.2005 00000000.00000000. \ Enable some PCI errors
- msr: 5000.2010 fff01120.001a021d. \ PCI timings
+ msr: 5000.2010 fff01120.001a021d. \ PCI timings - LB has the latency timer at max
msr: 5000.2011 04000300.00800f01. \ GLPCI_ARB - LX page 581
- msr: 5000.2014 00000000.00f000ff.
- msr: 5000.2015 30303030.30303030. \ Cache, prefetch, write combine a0000 - bffff
- msr: 5000.2016 30303030.30303030. \ Cache, prefetch, write combine c0000 - dffff
- msr: 5000.2017 34343434.30303030. \ Cache, prefetch, write combine e0000 - fffff, write protect f0000 - fffff
+
+\ I don't think we need to do anything special for the DOS hole from PCI
+\ msr: 5000.2014 00000000.00f000ff. \ Fixed region enables - f, b, and a
+\ msr: 5000.2015 30303030.30303030. \ Cache, prefetch, write combine a0000 - bffff
+\ msr: 5000.2016 30303030.30303030. \ Cache, prefetch, write combine c0000 - dffff
+\ msr: 5000.2017 34343434.30303030. \ Cache, prefetch, write combine e0000 - fffff, write protect f0000 - fffff
+
msr: 5000.2018 000ff000.00000130. \ Cache PCI DMA to low memory 0 .. fffff
\ msr: 5000.2019 0f7ff000.00100130. \ Cache PCI DMA to high memory - Memsize dependent
\ msr: 5000.201a 4041f000.40400120.
\ msr: 5000.201a 00000000.00000000. \ Off - default
msr: 5000.201b 00000000.00000000.
msr: 5000.201c 00000000.00000000.
- msr: 5000.201e 00000000.00000f00.
+ msr: 5000.201e 00000000.00000f00. \ PCI function number for MSR accesses to VP port
msr: 5000.201f 00000000.0000004b.
\ We don't need posted I/O writes to IDE, as we have no IDE
-\ clockgating
-\ msr: 5400.2004 00000000.00000000. \ Clock gating - default
-\ msr: 5400.2004 00000000.00000003. \ Clock gating
+\ VIP
+\ msr: 5400.2004 00000000.00000005. \ Clock gating - default
+\ AES
+\ msr: 5800.2002 00000007.00000007. \ SMI mask - default is all off
+\ msr: 5800.2004 00000000.00000015. \ Clock gating - default
+
\ chipsetinit(nb);
\ Set the prefetch policy for various devices
@@ -472,23 +482,26 @@
\ setup_gx2();
\ Graphics init
- msr: a000.2001 00000000.0fd60000. \ CBASE field is FB addr + 6M
+ msr: a000.2001 00000000.0fde0000. \ CBASE field is FB addr + 14M, fbsize
msr: a000.2002 00000001.00000001. \ Disable GP SMI
msr: a000.2003 00000003.00000003. \ Disable GP ERR
msr: a000.2004 00000000.00000001. \ Clock gating
msr: 8000.2001 00000000.00000720. \ VG config (priority)
- msr: 8000.2002 00001fff.00001fff. \ Disable SMIs
+ msr: 8000.2002 1001ffff.1001ffff. \ Disable SMIs
msr: 8000.2003 0000003f.0000003f. \ Disable ERRs
\ msr: 8000.2004 00000000.00000000. \ Clock gating - default
\ msr: 8000.2004 00000000.00000055. \ Clock gating
- msr: 8000.2011 00000000.00000001. \ VG SPARE - VG fetch state machine hardware fix off
- msr: 8000.2012 00000000.06060202. \ VG DELAY
+ msr: 8000.2011 00000000.00000042. \ VG SPARE - VG fetch state machine hardware fix off
+ msr: 8000.2012 00000000.00000302. \ VG DELAY
\ msr: 4c00.0015 00000037.00000001. \ MCP DOTPLL reset; unnecessary because of later video init
\ More GLCP stuff
- msr: 4c00.000f f2f100ff.56960444. \ I/O buffer delay controls
- msr: 4c00.0016 00000000.00000000. \ Turn off debug clock
+ msr: 4c00.000f f2f100ff.56960444. \ I/O buffer delay controls - LB uses 82f1.00aa.5696.0444
+ \ Our value has lower drive for mem signals and more delay for BA, MA, CKE, CS, RAS, CAS, WE
+
+ msr: 4c00.0016 00000000.00000000. \ Turn off debug clock - LB has 2 (default, GLIU1 to debug logic)
+\ msr: 4c00.001e 00000000.0000603c. \ Processor throttle off delay - LB values
msr: 4c00.2004 00000000.00000015. \ Hardware clock gating for everything (Insyde uses 0x14)
msr: 5000.2014 00000000.00ffffff. \ Enables PCI access to low mem
@@ -642,7 +655,7 @@
h# fd00.0000 h# 84 dc-base + l! \ GLIU0 Memory offset
h# fd00.0000 h# 4c gp-base + l! \ GP base
- h# fd80.0000 h# 460 vp-base + l! \ Flat panel base
+ h# fd80.0000 h# 460 vp-base + l! \ Flat panel base (reserved on LX)
\ VGdata.hw_vga_base = h# fd7.c000
\ VGdata.hw_cursor_base = h# fd7.bc00
Modified: cpu/x86/pc/olpc/romreset.bth
===================================================================
--- cpu/x86/pc/olpc/romreset.bth 2007-05-04 06:56:57 UTC (rev 350)
+++ cpu/x86/pc/olpc/romreset.bth 2007-05-04 07:00:17 UTC (rev 351)
@@ -124,12 +124,12 @@
\ sdram_set_spdregisters(),auto.c
\ The LX devel board has only 512M ROM, but assigning 1M of address space is harmless
- 25fff002.10f00000. 1808 set-msr \ 1M ROM at fff0.0000, system RAM limit at 0f00.0000
- 2000000e.fff00100. 10000028 set-msr \ Top of memory at 0eff.ffff
- 212000fd.ffffd000. 10000029 set-msr \ Frame buffer at PA fd00.0000 maps to RAM at 0f00.0000
+ 25fff002.10f00000. 1808 set-msr \ 1M ROM at fff0.0000, system RAM limit at 0f00.0000, fbsize
+ 2000000e.fff00100. 10000028 set-msr \ Top of memory at 0eff.ffff, fbsize
+ 212000fd.ffffd000. 10000029 set-msr \ Frame buffer at PA fd00.0000 maps to RAM at 0f00.0000, fbsize
10076013.00005040. 20000018 set-msr \ DIMM1 empty, DIMM0 256 MB, 1 module bank, 8K pages
2000000e.fff00100. 4000002c set-msr \ DMA to memory from 1M to RAM limit at 0f00.0000
- 0efff000.00100130. 50002019 set-msr \ PCI DMA to memory from 1M to RAM limit at 0f00.0000
+ 0efff000.00100130. 50002019 set-msr \ PCI DMA to memory from 1M to RAM limit at 0f00.0000, fbsize
\ 20000019 rmsr \ SDRAM timing and mode program
00000000.2814d352. 00001981 set-msr \ Memory delay values
Modified: cpu/x86/pc/olpc/vsapci.fth
===================================================================
--- cpu/x86/pc/olpc/vsapci.fth 2007-05-04 06:56:57 UTC (rev 350)
+++ cpu/x86/pc/olpc/vsapci.fth 2007-05-04 07:00:17 UTC (rev 351)
@@ -34,7 +34,7 @@
ff800000 , fffff000 , fffff000 , fffff000 ,
0 , 0 , 0 , 0 ,
- 30100b , 2200003 , 3000000 , 0 ,
+ 30100b , 2200002 , 3000000 , 8 ,
fd000000 , fe000000 , fe004000 , fe008000 , \ FB, GP, VG, DF
0 , 0 , 0 , 30100b , \ VIP (LX only)
0 , 0 , 0 , 0 ,
@@ -58,13 +58,13 @@
ffffc000 , 0 , 0 , 0 ,
0 , 0 , 0 , 0 ,
- 20281022 , 2a00006 , 10100000 , 8 ,
+ 20821022 , 2a00006 , 10100000 , 8 ,
fe010000 , 0 , 0 , 0 , \ I/O BAR - base of virtual registers
0 , 0 , 0 , 20821022 ,
+ 0 , 0 , 0 , 10e , \ INTA, IRQ 14
0 , 0 , 0 , 0 ,
0 , 0 , 0 , 0 ,
0 , 0 , 0 , 0 ,
- 0 , 0 , 0 , 0 ,
0 [if] \ Turned off
create nand-hdr \ Doesn't appear as a PCI device, and kernel doesn't care
@@ -197,12 +197,14 @@
lx? if
\ Amend the fake PCI headers for the LX settings
- h# 281022 nb-hdr h# 20 + l! \ Vendor/device ID - AMD
+ h# 20801022 nb-hdr h# 20 + l! \ Vendor/device ID - AMD
+ h# 20801022 nb-hdr h# 4c + l! \ Vendor/device ID - AMD
- h# ff000000 gxfb-hdr h# 0 + l! \ BAR0 MASK - FB
+ h# ff000008 gxfb-hdr h# 0 + l! \ BAR0 MASK - FB
h# ffffc000 gxfb-hdr h# 10 + l! \ BAR4 MASK - VIP
h# 20811022 gxfb-hdr h# 20 + l! \ Vendor/device ID - AMD
h# fe00c000 gxfb-hdr h# 40 + l! \ BAR4 address - VIP
+ h# 20811022 gxfb-hdr h# 4c + l! \ Vendor/device ID - AMD
h# 10e gxfb-hdr h# 5c + w! \ Interrupt pin and line - INTA, IRQ 14
then
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