[openfirmware] r895 - cpu/x86/pc/neptune
svn at openfirmware.info
svn at openfirmware.info
Thu Aug 28 11:07:37 CEST 2008
Author: wmb
Date: 2008-08-28 11:07:37 +0200 (Thu, 28 Aug 2008)
New Revision: 895
Modified:
cpu/x86/pc/neptune/config.fth
cpu/x86/pc/neptune/fw.bth
cpu/x86/pc/neptune/rmstart.fth
Log:
Neptune - added PLL autoconfiguration based on BOOTSTRAP bits.
Modified: cpu/x86/pc/neptune/config.fth
===================================================================
--- cpu/x86/pc/neptune/config.fth 2008-08-28 09:06:50 UTC (rev 894)
+++ cpu/x86/pc/neptune/config.fth 2008-08-28 09:07:37 UTC (rev 895)
@@ -33,7 +33,7 @@
create jffs2-support
create use-elf
-\ create lx-pll-autoconfig \ enable pll autoconfiguration from bootstrap pin
+create lx-pll-autoconfig \ enable pll autoconfiguration from bootstrap pin
create use-memtest86
\ create use-timestamp-counter \ Use CPU's timestamp counter for timing ...
Modified: cpu/x86/pc/neptune/fw.bth
===================================================================
--- cpu/x86/pc/neptune/fw.bth 2008-08-28 09:06:50 UTC (rev 894)
+++ cpu/x86/pc/neptune/fw.bth 2008-08-28 09:07:37 UTC (rev 895)
@@ -222,6 +222,7 @@
devalias nfs net//obp-tftp:last//nfs
fload ${BP}/cpu/x86/pc/boot.fth
+fload ${BP}/cpu/x86/pc/linux.fth
h# 3ea constant usb-port-power-map \ USB4:PWR2 USB3:PWR1 USB2:PWR1 USB1:PWR1
fload ${BP}/dev/geode/usb.fth
@@ -286,8 +287,6 @@
fload ${BP}/ofw/gui/loadmenu.fth
\ fload ${BP}/ofw/gui/insticon.fth
-fload ${BP}/cpu/x86/pc/linux.fth
-
\ Use values like these if you want to boot directly instead of through an intermediate script
" u:\boot\bzImage" ' boot-device set-config-string-default
\ " console=uart,io,0x3f8,115200" ' boot-file set-config-string-default
Modified: cpu/x86/pc/neptune/rmstart.fth
===================================================================
--- cpu/x86/pc/neptune/rmstart.fth 2008-08-28 09:06:50 UTC (rev 894)
+++ cpu/x86/pc/neptune/rmstart.fth 2008-08-28 09:07:37 UTC (rev 895)
@@ -135,8 +135,41 @@
al bl mov
op: h# fc00.0000 # ax and 0= if \ Start the PLL if not already on
-[ifndef] lx-pll-autoconfig
- 0 [if]
+[ifdef] lx-pll-autoconfig
+
+ \ PLL autoconfiguration from bootstrap pins
+ \ EDX,EAX contains the value of MSR 4c00.0014 - RSTPLL
+ \ The bootstrap bits are 7..1
+
+ al bl mov \ Get a copy of the BOOTSTRAP bits
+ h# 1 # bl shr \ Shift out CHIP_RESET and align the field at bit 0
+
+ \ The bl comparison values are the BOOTSTRAP pin settings.
+ \ The h#40 bit is 0 for 33 MHz PCI clock, 1 for 66 MHz.
+ \ The dx values are from table 6-87 in the LX databook,with h# 41 added to
+ \ set both predivider bits (for 66 MHz PCI clock).
+
+ \ The comparison values below correspond to the validated timings from the table in the schematic.
+
+ h# 4c # bl cmp 0= if op: h# 0000.04d7 # dx mov else \ Core 400 Mem 333
+ h# 54 # bl cmp 0= if op: h# 0000.05db # dx mov else \ Core 466 Mem 400
+ h# 55 # bl cmp 0= if op: h# 0000.03dd # dx mov else \ Core 500 Mem 266
+ h# 5e # bl cmp 0= if op: h# 0000.04e3 # dx mov else \ Core 600 Mem 333
+ h# 5f # bl cmp 0= if op: h# 0000.05e3 # dx mov else \ Core 600 Mem 333
+
+ \ The default value below is for Mitch's test board whose bootstrap value
+ \ h# 48 should mean 366/200, but that board is really 500/333
+
+ op: h# 0000.04dd # dx mov \ Core 500 Mem 333
+
+ then then then then then \ Same number of then's as number of if's above
+
+ op: h# 0000.1800 invert # ax and \ Clear bypass bits
+ op: h# 04ff.6001 # ax or \ Set SWFLAGS=1, HOLD_COUNT=ff, GLIUPD,COREPD,CHIP_RESET
+ wrmsr \ Start the PLL and reset the CPU
+
+[else]
+ 0 [if]
\ pll manual configuration
rdmsr \ Get base MSR value with divisors
op: h# 07de.0000 # ax or \ Set the startup time (de) and breadcrumb (4)
@@ -148,8 +181,9 @@
op: h# 0000.1800 invert # ax and \ Turn off the BYPASS bits
h# 6001 # ax or \ Set PD, RESETPLL
+ wrmsr \ Start the PLL and reset the CPU
- [else]
+ [else]
\ pll manual configuration (easier version..)
\ op: h# 0000.03DD # dx mov \ 500 MHz + 266 MHz
@@ -159,22 +193,13 @@
op: h# 0000.04DD # dx mov \ 500 MHz + 333 MHz
\ op: h# 0000.05DD # dx mov \ 500 MHz + 400 MHz
-
- \ op: h# 04DE.6001 # ax mov
- op: h# 04FF.6001 # ax mov \ longer reset time for pll startup
+ \ op: h# 04DE.6001 # ax mov
+ op: h# 04FF.6001 # ax mov \ longer reset time for pll startup
+ wrmsr \ Start the PLL and reset the CPU
- [then]
+ [then]
-[else]
- \ pll auto configuration from bootstrap pin
-
- op: h# 00ff.0000 invert # ax and
- op: h# 00de.0000 # ax or
-
- op: h# 0000.1800 invert # ax and
- op: h# 0700.6001 # ax or
[then]
- wrmsr \ Start the PLL and reset the CPU
then
\ Return to here after the reset
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