[openfirmware] r1154 - in cpu/x86/pc/olpc: . via via/build
svn at openfirmware.info
svn at openfirmware.info
Thu Apr 23 10:06:39 CEST 2009
Author: wmb
Date: 2009-04-23 10:06:39 +0200 (Thu, 23 Apr 2009)
New Revision: 1154
Added:
cpu/x86/pc/olpc/via/
cpu/x86/pc/olpc/via/addrs.fth
cpu/x86/pc/olpc/via/build/
cpu/x86/pc/olpc/via/build/Makefile
cpu/x86/pc/olpc/via/config.fth
cpu/x86/pc/olpc/via/devices.fth
cpu/x86/pc/olpc/via/fw.bth
cpu/x86/pc/olpc/via/old-reg-settings.fth
cpu/x86/pc/olpc/via/olpc.bth
cpu/x86/pc/olpc/via/pcinode.fth
cpu/x86/pc/olpc/via/probemem.fth
cpu/x86/pc/olpc/via/rmstart.bth
cpu/x86/pc/olpc/via/rmstart.fth
cpu/x86/pc/olpc/via/romreset.bth
cpu/x86/pc/olpc/via/smbus.fth
cpu/x86/pc/olpc/via/sourceurl.fth
cpu/x86/pc/olpc/via/southbridge.fth
cpu/x86/pc/olpc/via/usb.fth
cpu/x86/pc/olpc/via/versions.fth
Log:
Initial checking of OLPC Via CPU support
Added: cpu/x86/pc/olpc/via/addrs.fth
===================================================================
--- cpu/x86/pc/olpc/via/addrs.fth (rev 0)
+++ cpu/x86/pc/olpc/via/addrs.fth 2009-04-23 08:06:39 UTC (rev 1154)
@@ -0,0 +1,92 @@
+\ See license at end of file
+purpose: Establish address and I/O configuration definitions
+
+[ifdef] rom-loaded
+[ifdef] demo-board
+h# fff8.0000 constant rom-pa \ Physical address of boot ROM
+h# 8.0000 constant /rom \ Size of boot ROM
+\ h# fffe.0000 constant rom-pa \ Physical address of boot ROM
+\ h# 2.0000 constant /rom \ Size of boot ROM
+rom-pa constant dropin-base
+[else]
+h# fff0.0000 constant rom-pa \ Physical address of boot ROM
+h# 10.0000 constant /rom \ Size of boot ROM
+rom-pa h# 1.0000 + constant dropin-base
+[then]
+
+h# 8.0000 constant dropin-size
+
+dropin-base h# 20 + constant ResetBase \ Location of "reset" dropin in ROM
+
+h# 1bc0.0000 value fw-pa \ Changed in probemem.fth
+h# 20.0000 constant /fw-ram
+h# 40.0000 constant /fw-area
+[then]
+
+h# 80.0000 constant def-load-base \ Convenient for initrd
+
+\ The heap starts at RAMtop, which on this system is "fw-pa /fw-ram +"
+
+\ We leave some memory in the /memory available list above the heap
+\ for DMA allocation by the sound and USB driver. OFW's normal memory
+\ usage thus fits in one 4M page-directory mapping region.
+
+h# 18.0000 constant heap-size
+
+h# 900.0000 constant dma-size
+fw-pa dma-size - constant dma-base
+
+h# f.0000 constant suspend-base \ In the DOS hole
+h# f.0008 constant resume-entry
+h# f.1000 constant resume-data
+
+\ If you change these, also change {g/l}xmsrs.fth and {g/l}xearly.fth
+h# fd00.0000 constant fw-map-base
+h# ffc0.0000 constant fw-map-limit
+
+h# d000.0000 constant fb-pci-base
+h# f000.0000 constant gfx-pci-base
+h# fe01.a000 constant ohci-pci-base
+h# fe01.b000 constant ehci-pci-base
+h# fe02.4000 constant sd-pci-base
+h# fe02.8000 constant camera-pci-base
+
+h# 9.fc00 constant 'ebda \ Extended BIOS Data Area, which we co-opt for our real-mode workspace
+
+h# e0000 constant rsdp-adr
+h# e0040 constant rsdt-adr
+h# e0080 constant fadt-adr
+h# e0180 constant facs-adr
+h# e01c0 constant dbgp-adr
+h# fc000 constant dsdt-adr
+h# fd000 constant ssdt-adr
+
+h# 3e.0000 constant inflate-base
+h# 30.0000 constant workspace
+
+fload ${BP}/cpu/x86/pc/virtaddr.fth
+
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/x86/pc/olpc/via/build/Makefile
===================================================================
--- cpu/x86/pc/olpc/via/build/Makefile (rev 0)
+++ cpu/x86/pc/olpc/via/build/Makefile 2009-04-23 08:06:39 UTC (rev 1154)
@@ -0,0 +1,44 @@
+OS := $(shell uname)
+
+CPUDIR=../../../..
+BASEDIR := $(shell cd ${CPUDIR}/../..; pwd;)
+TAGFILES= ${CPUDIR}/build/*.tag *.tag
+CLIENTDIR=${BASEDIR}/clients
+CLIENTPROGS=${CLIENTDIR}/memtest86/memtest ${CLIENTDIR}/emacs/x86/emacs
+
+all: olpc.rom tags
+
+fw.tag: olpc.rom
+
+tags: fw.tag
+ @${BASEDIR}/forth/lib/toctags ${BASEDIR} ${TAGFILES}
+
+ofw.elf: FORCE build ${CPUDIR}/build/inflate.bin
+ ./build $@
+
+olpc.rom: FORCE build ${CPUDIR}/build/inflate.bin ${CLIENTPROGS}
+ ./build $@
+
+${CPUDIR}/${OS}/forth:
+ @make -C ${CPUDIR}/${OS} forth
+
+${CPUDIR}/build/inflate.bin:
+ @make -C ${CPUDIR}/build inflate.bin
+
+${CLIENTDIR}/memtest86/memtest:
+ @make -C ${CLIENTDIR}/memtest86 memtest
+
+${CLIENTDIR}/emacs/x86/emacs:
+ @make -C ${CLIENTDIR}/emacs/x86 emacs
+
+build: ${CPUDIR}/${OS}/forth
+ @ln -sf ${CPUDIR}/${OS}/forth build
+
+clean:
+ rm -f *.dic *.log headers *~ *.elf *.di *.img builton.fth build *.rom ec.version olpc.version
+
+clean-all: clean
+ @make -C ${CPUDIR}/build clean
+ @make -C ${CPUDIR}/${OS} clean
+
+.PHONY: FORCE clean all clean-all
Added: cpu/x86/pc/olpc/via/config.fth
===================================================================
--- cpu/x86/pc/olpc/via/config.fth (rev 0)
+++ cpu/x86/pc/olpc/via/config.fth 2009-04-23 08:06:39 UTC (rev 1154)
@@ -0,0 +1,63 @@
+\ See license at end of file
+purpose: Establish configuration definitions
+
+create olpc \ OLPC-specific build
+
+create demo-board
+
+\ --- The environment that "boots" us ---
+\ - Image Format - Example Media - previous stage bootloader
+
+\ - OBMD format - ROM - direct boot from ROM
+create rom-loaded
+
+\ create virtual-mode
+create addresses-assigned \ Define if base addresses are already assigned
+create serial-console \ Define to default to serial port for console
+create pc
+create linux-support
+create use-elf
+
+\ create use-timestamp-counter \ Use CPU's timestamp counter for timing ...
+ \ ... this is worthwhile if your CPU has one.
+
+create resident-packages
+\ create use-watch-all
+\ create use-root-isa \ If defined, isa node is in the devtree root, not under /pci
+create no-floppy-node
+create no-com2-node
+create no-lpt-node
+create use-pci-isa
+create basic-isa
+create isa-dma-only
+create use-ega
+create save-msrs
+
+create use-null-nvram \ Don't store configuration variables
+\ create use-flash-nvram \ Store configuration variables in firmware FLASH
+
+fload ${BP}/cpu/x86/pc/olpc/via/addrs.fth
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/x86/pc/olpc/via/devices.fth
===================================================================
--- cpu/x86/pc/olpc/via/devices.fth (rev 0)
+++ cpu/x86/pc/olpc/via/devices.fth 2009-04-23 08:06:39 UTC (rev 1154)
@@ -0,0 +1,386 @@
+\ See license at end of file
+purpose: Load device drivers according to configuration definitions
+
+0 0 " " " /" begin-package
+ fload ${BP}/cpu/x86/pc/mappci.fth \ Map PCI to root
+ fload ${BP}/dev/pcibus.fth \ Generic PCI bus package
+ fload ${BP}/cpu/x86/pc/olpc/via/pcinode.fth \ System-specific words for PCI
+end-package
+stand-init: PCI host bridge
+ " /pci" " init" execute-device-method drop
+;
+
+fload ${BP}/dev/pciprobe.fth \ Generic PCI probing
+
+\ Use the CPU chip's Time Stamp Counter for timing; it does just what we want
+fload ${BP}/cpu/x86/tsc.fth
+
+stand-init:
+ d# 1,500,000,000 " VIA,C7"
+
+ " /cpu" find-device ( cpu-clock-hz model$ )
+ " model" string-property ( cpu-clock-hz )
+ dup " clock-frequency" integer-property ( cpu-clock-hz )
+ device-end ( cpu-clock-hz )
+
+ d# 2000 / dup to ms-factor ( cpu-clock-khz )
+ d# 1000 / to us-factor ( )
+;
+
+[ifdef] use-ega
+0 0 " " " /" begin-package
+ fload ${BP}/dev/egatext.fth
+end-package
+\ devalias screen /ega-text
+[then]
+
+[ifdef] use-root-isa
+0 0 " " " /" begin-package
+ fload ${BP}/cpu/x86/pc/isabus.fth \ ISA Bus Bridge under root node
+end-package
+[then]
+
+[ifdef] use-pci-isa
+
+[ifdef] addresses-assigned
+[ifdef] use-pci-isa
+\ This must precede isamisc.fth in the load file, to execute it first
+fload ${BP}/cpu/x86/pc/moveisa.fth
+[then]
+[then]
+
+0 0 " 0" " /pci" begin-package
+ fload ${BP}/dev/pci/isa.fth \ ISA bus bridge under PCI node
+ fload ${BP}/dev/pci/isamisc.fth
+end-package
+
+[then]
+
+fload ${BP}/cpu/x86/pc/olpc/timertest.fth \ Selftest for PIT timer
+
+1 [if]
+warning @ warning off
+: probe-pci ( -- )
+ probe-pci
+ " /pci" " make-interrupt-map" execute-device-method drop
+;
+warning !
+
+\ Create the top-level device node to access the entire boot FLASH device
+0 0 " fff00000" " /" begin-package
+ " flash" device-name
+
+ h# 10.0000 value /device
+ h# 10.0000 constant /device-phys
+ my-address my-space /device-phys reg
+ fload ${BP}/dev/flashpkg.fth
+ fload ${BP}/dev/flashwrite.fth
+end-package
+
+\ Create a node below the top-level FLASH node to accessing the portion
+\ containing the dropin modules
+0 0 " 80000" " /flash" begin-package
+ " dropins" device-name
+
+ h# 70000 constant /device
+ fload ${BP}/dev/subrange.fth
+end-package
+
+devalias dropins /dropins
+
+\ Create a pseudo-device that presents the dropin modules as a filesystem.
+fload ${BP}/ofw/fs/dropinfs.fth
+
+\ This devalias lets us say, for example, "dir rom:"
+devalias rom /dropin-fs
+
+fload ${BP}/cpu/x86/forthint.fth \ Low-level interrupt handling code
+fload ${BP}/dev/isa/irq.fth \ ISA interrupt dispatcher
+fload ${BP}/cpu/x86/pc/isatick.fth \ Use ISA timer as the alarm tick timer
+
+dev /interrupt-controller
+irq-vector-base to vector-base0
+vector-base0 8 + to vector-base1
+device-end
+
+[ifdef] resident-packages
+support-package: 16550
+fload ${BP}/dev/16550pkg/16550.fth \ Serial port support package
+end-support-package
+[then]
+
+fload ${BP}/dev/pci/isaall.fth
+\ We don't need a serial selftest because the serial port is internal only
+\ and the selftest turns off the diag device
+dev /serial warning @ warning off : selftest false ; warning ! device-end
+devalias com1 /isa/serial at i3f8:115200
+devalias mouse /isa/8042/mouse
+devalias d disk
+devalias n nand
+devalias sd /sd/disk
+
+[ifndef] demo-board
+.( Removing ctlr-selftest from 8042 open !!!) cr
+dev /8042
+ patch false ctlr-selftest open
+device-end
+[then]
+
+0 0 " i70" " /isa" begin-package \ Real-time clock node
+ fload ${BP}/dev/ds1385r.fth
+ 8 encode-int 0 encode-int encode+ " interrupts" property
+ 2 encode-int " device#" property
+end-package
+stand-init: RTC
+ " /rtc" open-dev clock-node !
+;
+
+fload ${BP}/cpu/x86/pc/cpunode.fth
+fload ${BP}/cpu/x86/k6cputest.fth \ Burnin test for K6 CPU
+
+0 [if]
+fload ${BP}/ofw/console/bailout.fth
+stand-init: Keyboard overrides
+ ?bailout
+;
+[then]
+
+fload ${BP}/forth/lib/pattern.fth \ Text string pattern matching
+fload ${BP}/forth/lib/tofile.fth \ to-file and append-to-file
+\ XXX remove the OS file commands from tools.dic
+fload ${BP}/ofw/core/filecmds.fth \ File commands: dir, del, ren, etc.
+
+fload ${BP}/cpu/x86/pc/olpc/cmos.fth \ CMOS RAM indices are 1f..ff , above RTC
+
+devalias nand /nandflash
+devalias mtd /nandflash
+
+[ifdef] use-null-nvram
+\ For not storing configuration variable changes across reboots ...
+\ This is useful for "turnkey" systems where configurability would
+\ increase support costs.
+
+fload ${BP}/cpu/x86/pc/nullnv.fth
+stand-init: Null-NVRAM
+ " /null-nvram" open-dev to nvram-node
+ ['] init-config-vars catch drop
+;
+[then]
+
+[ifdef] use-flash-nvram
+\ For configuration variables stored in a sector of the boot FLASH ...
+
+\ Create a node below the top-level FLASH node to access the portion
+\ containing the configuration variables.
+0 0 " d0000" " /flash" begin-package
+ " nvram" device-name
+
+ h# 10000 constant /device
+ fload ${BP}/dev/subrange.fth
+end-package
+
+stand-init: NVRAM
+ " /nvram" open-dev to nvram-node
+ ['] init-config-vars catch drop
+;
+[then]
+
+\ Create the alias unless it already exists
+: $?devalias ( alias$ value$ -- )
+ 2over not-alias? if $devalias exit then ( alias$ value$ alias$ )
+ 2drop 4drop
+;
+
+: report-disk ( -- )
+ " /usb/disk" locate-device 0= if
+ drop
+ " disk" " /usb/disk" $devalias
+ exit
+ then
+ " /usb at f,4/disk" locate-device 0= if
+ ." Found USB 1.1 disk!" cr
+ drop
+ " disk" " /usb at f,4/disk" $devalias
+ exit
+ then
+;
+
+: report-keyboard ( -- )
+ " /usb at f,4/keyboard" locate-device 0= if
+ drop
+ " keyboard" " /usb at f,4/keyboard" $devalias
+ exit
+ then
+
+ \ In case the keyboard is behind a USB 2 hub
+ " /usb at f,5/keyboard" locate-device 0= if
+ drop
+ " keyboard" " /usb at f,5/keyboard" $devalias
+ then
+;
+
+fload ${BP}/cpu/x86/inoutstr.fth \ Multiple I/O port read/write
+fload ${BP}/dev/isa/diaguart.fth \ ISA COM port driver
+\ : inituarts ascii G uemit ascii o uemit ; \ They are already on
+
+h# 3f8 is uart-base
+fload ${BP}/forth/lib/sysuart.fth \ Use UART for key and emit
+
+[ifndef] save-flash
+: save-flash ;
+: restore-flash ;
+[then]
+
+\needs md5init fload ${BP}/ofw/ppp/md5.fth \ MD5 hash
+
+\ fload ${BP}/dev/geode/acpi.fth \ Power management
+
+[ifdef] use-ec
+fload ${BP}/dev/olpc/kb3700/ecspi.fth \ EC chip SPI FLASH access
+
+warning @ warning off
+: stand-init-io stand-init-io h# fff0.0000 to flash-base ;
+warning !
+
+fload ${BP}/dev/olpc/kb3700/ecserial.fth \ Serial access to EC chip
+
+fload ${BP}/dev/olpc/kb3700/ecio.fth \ I/O space access to EC chip
+
+fload ${BP}/cpu/x86/pc/olpc/boardrev.fth \ Board revision decoding
+[then]
+
+: cpu-mhz ( -- n )
+ " /cpu at 0" find-package drop ( phandle )
+ " clock-frequency" rot get-package-property if 0 exit then ( adr )
+ decode-int nip nip d# 1000000 /
+;
+
+[ifdef] use-ec
+stand-init: Date to EC
+ time&date d# 2000 - ['] ec-date! catch if 3drop then
+ 3drop
+;
+[then]
+
+[ifdef] use-wlan
+stand-init: Wireless reset
+ \ Hit the reset on the Marvell wireless. It sometimes (infrequently)
+ \ fails to enumerate after a power-cycle, and reset seems to fix it.
+ \ We need > 85 ms between wlan-reset and probe-usb, but console-start
+ \ takes about 200 mS, so we are okay.
+ atest? 0= if wlan-reset then
+;
+[then]
+
+[ifdef] use-ec
+stand-init: PCI properties
+ " /pci" find-device
+ board-revision h# b18 < if
+ d# 33,333,333
+ else
+ \ We switched to 66 MHz at B2
+ d# 66,666,667
+ then
+ " clock-frequency" integer-property
+ dend
+;
+[then]
+
+[ifdef] use-ec
+fload ${BP}/cpu/x86/pc/olpc/mfgdata.fth \ Manufacturing data
+fload ${BP}/cpu/x86/pc/olpc/mfgtree.fth \ Manufacturing data in device tree
+fload ${BP}/cpu/x86/pc/olpc/kbdtype.fth \ Export keyboard type
+
+fload ${BP}/dev/olpc/kb3700/battery.fth \ Battery status reports
+
+fload ${BP}/dev/olpc/spiflash/spiflash.fth \ SPI FLASH programming
+fload ${BP}/dev/olpc/spiflash/spiui.fth \ User interface for SPI FLASH programming
+fload ${BP}/dev/olpc/spiflash/recover.fth \ XO-to-XO SPI FLASH recovery
+
+: ofw-fw-filename$ " disk:\boot\olpc.rom" ;
+' ofw-fw-filename$ to fw-filename$
+[then]
+
+: +i encode-int encode+ ; : 0+i 0 +i ;
+
+[ifdef] Later
+fload ${BP}/cpu/x86/pc/olpc/via/gpioinit.fth
+fload ${BP}/cpu/x86/pc/olpc/via/chipinit.fth
+[then]
+
+0 0 " 1,0" " /pci" begin-package
+\ fload ${BP}/dev/olpc/dcon/dconsmb.fth \ SMB access to DCON chip
+\ fload ${BP}/dev/olpc/dcon/dcon.fth \ DCON control
+ fload ${BP}/dev/via/unichrome/loadpkg.fth \ Geode display
+
+ 0 0 encode-bytes
+ h# 8200.0810 +i 0+i fb-pci-base +i 0+i h# d000.0000 +i \ Frame buffer
+ h# 8200.0914 +i 0+i gfx-pci-base +i 0+i h# f000.0000 +i \ MMIO
+ " assigned-addresses" property
+end-package
+devalias screen /display
+also hidden d# 34 to display-height previous \ For editing
+[then]
+
+fload ${BP}/cpu/x86/adpcm.fth \ ADPCM decoding
+
+[ifdef] use-ec
+warning @ warning off
+: stand-init
+ stand-init
+ root-device
+ model-name$ 2dup model ( name$ )
+ " OLPC " encode-bytes 2swap encode-string encode+ " banner-name" property
+ board-revision " board-revision-int" integer-property
+ \ The "1-" removes the null byte
+ " SN" find-tag if 1- else " Unknown" then " serial-number" string-property
+ 8 ec-cmd-b@ dup " ec-version" integer-property
+
+ \ EC code API 56 and greater changes the version numbering
+ h# 56 >= if " Ver:" else " PQ2" then
+
+ h# fff0.0000 h# 1.0000 sindex dup 0>= if ( offset )
+ h# fff0.0000 + cscount ( name )
+ else
+ drop " UNKNOWN"
+ then
+ " ec-name" string-property
+
+ dend
+
+ " /openprom" find-device
+ h# ffff.ffc0 d# 16 " model" string-property
+
+ " sourceurl" find-drop-in if " source-url" string-property then
+ dend
+;
+warning !
+[then]
+
+[ifdef] Later
+fload ${BP}/cpu/x86/pc/olpc/micin.fth \ Microphone input AC/DC coupling
+[then]
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2006 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/x86/pc/olpc/via/fw.bth
===================================================================
--- cpu/x86/pc/olpc/via/fw.bth (rev 0)
+++ cpu/x86/pc/olpc/via/fw.bth 2009-04-23 08:06:39 UTC (rev 1154)
@@ -0,0 +1,737 @@
+purpose: Build Open Firmware for OLPC
+\ See license at end of file
+
+dictionary: ${BP}/cpu/x86/build/basefw.dic
+command: &x86forth &dictionary &this
+in: builton.fth
+build-now
+
+" fw.tag" r/w create-file drop tag-file !
+
+hex
+\ ' $report-name is include-hook
+
+fload ${BP}/cpu/x86/pc/olpc/via/config.fth
+
+: headerless ; : headers ; : headerless0 ;
+
+' (quit) to quit
+
+create debug-startup
+: \Tags [compile] \ ; immediate
+: \NotTags [compile] \ ; immediate
+
+: RAMbase ( -- adr ) fw-virt-base ;
+: RAMtop ( -- adr ) RAMbase /fw-ram + ;
+
+h# 00.0000 value dp-loc \ Set in patchboot
+: stacktop ( -- adr ) RAMtop ;
+: dict-limit ( -- adr ) RAMtop h# 06.0000 - ;
+
+\ XXX What we should do is pass in the top address in SP, and have
+\ boot.fth allocate the user area by subtracting user-size. But
+\ we need some way of finding it again for exception re-entry.
+\ prom-main-task is used in arch/pc/boot.fth . The constant
+\ value is wired into the assembly code
+stacktop user-size - constant prom-main-task \ user area for main task
+
+0 value load-limit \ Top address of area at load-base
+' 2drop to sync-cache
+
+def-load-base ' load-base set-config-int-default
+
+true ' fcode-debug? set-config-int-default
+\ false ' auto-boot? set-config-int-default
+
+[ifdef] serial-console
+" com1" ' output-device set-config-string-default
+" com1" ' input-device set-config-string-default
+[then]
+
+\ XXX should be loaded by basefw.bth
+fload ${BP}/cpu/x86/initpgm.fth \ Basic boot handler
+fload ${BP}/cpu/x86/msr.fth \ Access to machine specific registers
+
+: (cpu-arch ( -- adr len )
+ " architecture" ['] root-node get-package-property drop
+ get-encoded-string
+;
+' (cpu-arch to cpu-arch
+
+h# 1000 to pagesize
+d# 12 to pageshift
+
+dev /
+1 encode-int " #address-cells" property
+1 encode-int " #size-cells" property
+" OLPC" encode-string " architecture" property
+device-end
+
+\ Memory management services
+[ifdef] virtual-mode
+fload ${BP}/ofw/core/clntmem1.fth \ client services for memory
+[else]
+fload ${BP}/ofw/core/clntphy1.fth \ client services for memory
+\ : >physical ( va -- pa )
+\ dup fw-virt-base - fw-virt-size u< if ( va )
+\ fw-virt-base - fw-pa +
+\ then
+\ ;
+[then]
+fload ${BP}/ofw/core/memlist.fth \ Resource list common routines
+fload ${BP}/ofw/core/showlist.fth \ Linked list display tool
+fload ${BP}/ofw/core/allocph1.fth \ S Physical memory allocator
+fload ${BP}/ofw/core/availpm.fth \ Available memory list
+fload ${BP}/ofw/core/allocmor.fth \ Secondary allocator
+
+fload ${BP}/cpu/x86/pc/rootnode.fth \ Platform-specific root node changes
+
+fload ${BP}/cpu/x86/pc/olpc/port80.fth \ Port 80 debug messages
+
+[ifdef] Later
+fload ${BP}/dev/geode/gpio.fth \ Rudimentary GPIO driver
+[then]
+
+fload ${BP}/cpu/x86/pc/isaio.fth
+fload ${BP}/dev/pci/configm1.fth \ Generic PCI configuration access
+
+fload ${BP}/cpu/x86/pc/olpc/via/probemem.fth \ Memory probing
+
+[ifdef] virtual-mode
+fload ${BP}/cpu/x86/loadvmem.fth \ /mmu node
+
+stand-init: MMU
+ " /mmu" open-dev mmu-node !
+;
+fload ${BP}/cpu/x86/pc/initdict.fth \ Dynamic dictionary allocation
+[then]
+
+\ XXX should be elsewhere
+dev /client-services
+: chain ( len args entry size virt -- )
+ release ( len args entry )
+ h# 8000 alloc-mem h# 8000 + (init-program) ( len args )
+ to %ebx to %ecx
+ go
+;
+device-end
+
+fload ${BP}/cpu/x86/crc32.fth \ Assembly language Zip CRC calculation
+fload ${BP}/forth/lib/crc32.fth \ High-level portion of CRC calculation
+
+[ifdef] resident-packages
+
+[ifdef] use-ufs
+support-package: ufs-file-system
+ fload ${BP}/ofw/fs/ufs/ufs.fth \ Unix file system
+end-support-package
+[then]
+
+[ifdef] linux-support
+\needs unix-seconds> fload ${BP}/ofw/fs/unixtime.fth \ Unix time calculation
+support-package: ext2-file-system
+ fload ${BP}/ofw/fs/ext2fs/ext2fs.fth \ Linux file system
+end-support-package
+[then]
+
+[ifdef] jffs2-support
+\needs unix-seconds> fload ${BP}/ofw/fs/unixtime.fth \ Unix time calculation
+support-package: jffs2-file-system
+ fload ${BP}/ofw/fs/jffs2/jffs2.fth \ Journaling flash file system 2
+end-support-package
+[then]
+
+support-package: zip-file-system
+ fload ${BP}/ofw/fs/zipfs.fth \ Zip file system
+end-support-package
+
+support-package: dropin-file-system
+ fload ${BP}/ofw/fs/dropinfs.fth \ Dropin file system
+end-support-package
+[then]
+
+support-package: minix-file-system
+ fload ${BP}/ofw/fs/minix.fth \ Minix3 file system
+end-support-package
+
+fload ${BP}/ofw/core/osfile.fth \ For testing
+
+\ Load file format handlers
+
+: call32 ;
+
+fload ${BP}/ofw/core/allocsym.fth \ Allocate memory for symbol table
+fload ${BP}/ofw/core/symcif.fth
+fload ${BP}/ofw/core/symdebug.fth
+: release-load-area ( boundary-adr -- ) drop ;
+
+[ifdef] use-elf
+fload ${BP}/ofw/elf/elf.fth
+fload ${BP}/ofw/elf/elfdebug.fth
+[ifdef] virtual-mode
+\ Depends on the assumption that physical memory is mapped 1:1 already
+: (elf-map-in) ( va size -- ) 0 mem-claim drop ;
+[else]
+: (elf-map-in) ( va size -- ) 2drop ;
+[then]
+' (elf-map-in) is elf-map-in
+[then]
+
+\ Reboot and re-entry code
+fload ${BP}/cpu/x86/pc/reboot.fth \ Restart the client program
+fload ${BP}/cpu/x86/pc/reenter.fth \ Various entries into Forth
+
+headerless
+[ifdef] virtual-mode
+: (initial-heap) ( -- adr len ) sp0 @ ps-size - dict-limit tuck - ;
+[else]
+: (initial-heap) ( -- adr len ) RAMtop heap-size ;
+[then]
+' (initial-heap) is initial-heap
+headers
+
+" /openprom" find-device
+ " FirmWorks,3.0" encode-string " model" property
+device-end
+
+[ifdef] virtual-mode
+fload ${BP}/cpu/x86/pc/mmusetup.fth \ Initial values for MMU lists
+dev /mmu
+: claim-rom ( -- )
+ (initial-claim)
+ rom-pa h# ffff.0000 over - claim-virtual drop \ ROM 1-1 map
+;
+' claim-rom to initial-claim
+dend
+[then]
+
+: background-rgb ( -- r g b ) h# ff h# ff h# ff ;
+
+fload ${BP}/cpu/x86/pc/olpc/via/devices.fth
+
+fload ${BP}/cpu/x86/pc/olpc/countdwn.fth \ Startup countdown
+
+fload ${BP}/dev/scsi/probscsi.fth \ probe-scsi and probe-scsi-all
+
+true ' local-mac-address? set-config-int-default
+[ifdef] resident-packages
+support-package: nfs
+ fload ${BP}/ofw/fs/nfs/loadpkg.fth
+end-support-package
+
+[then]
+devalias nfs net//obp-tftp:last//nfs
+
+fload ${BP}/cpu/x86/pc/boot.fth
+fload ${BP}/cpu/x86/pc/linux.fth
+
+
+fload ${BP}/cpu/x86/pc/olpc/via/usb.fth
+
+false to stand-init-debug?
+\ true to stand-init-debug?
+
+hex
+: i-key-wait ( ms -- pressed? )
+ ['] key? (see)
+ cr ." Type 'i' to interrupt stand-init sequence" cr
+ 0 do
+ key? if
+ key upc ascii I = if true unloop exit then
+ then
+ 1 ms
+ loop
+ false
+;
+
+[ifdef] Later
+false value secure?
+
+: protect-fw ( -- ) secure? if ec-indexed-io-off then ;
+[then]
+
+\ stand-init-debug? [if]
+warning @ warning off
+: init
+\ initial-heap add-memory
+ init
+
+ standalone? if
+ disable-interrupts
+interact
+[ifdef] Later
+ d# 300
+ i-key-wait if
+ [ifdef] Later
+ protect-fw
+ [then]
+ ." Interacting" cr hex interact
+ then
+
+ [ifdef] Later
+ setup
+ [then]
+[else]
+ cr
+[then]
+ then
+;
+\ warning !
+[then]
+
+: (.firmware) ( -- )
+ ." Open Firmware " .built cr
+ ." Copyright 1999 FirmWorks All Rights Reserved" cr
+;
+' (.firmware) to .firmware
+
+: probe-all ( -- )
+ probe-pci
+ probe-usb
+;
+
+fload ${BP}/ofw/gui/bmptools.fth
+fload ${BP}/dev/null.fth
+fload ${BP}/ofw/core/bailout.fth
+
+[ifdef] Later
+[ifdef] olpc
+\ GUI
+false value gui-safeboot?
+
+\ FIXME need to implement user-ok to lockout ok prompt
+: 2tuck ( d1 d2 -- d2 d1 d2 ) 2swap 2over ;
+false value fru-test?
+: user-ok "ok" ; \ This is supposed to check for authorization
+true value user-mode?
+
+fload ${BP}/cpu/x86/pc/olpc/banner.fth
+[then]
+
+fload ${BP}/ofw/gui/loadmenu.fth
+fload ${BP}/cpu/x86/pc/olpc/disptest.fth
+\ fload ${BP}/ofw/gui/insticon.fth
+
+[ifdef] olpc
+: setup-for-linux ( -- )
+ [ ' linux-hook behavior compile, ] \ Chain to old behavior
+ vpci-devices-on \ Do this after quieting USB
+;
+' setup-for-linux to linux-hook
+: screen-#lines ( -- n )
+ screen-ih 0= if default-#lines exit then
+ screen-ih package( #lines )package
+;
+' screen-#lines to lines/page
+
+fload ${BP}/cpu/x86/pc/olpc/help.fth
+fload ${BP}/cpu/x86/pc/olpc/gui.fth
+fload ${BP}/cpu/x86/pc/olpc/suspend.fth \ Suspend/resume setup
+fload ${BP}/dev/olpc/keyboard/selftest.fth \ Keyboard diagnostic
+fload ${BP}/dev/olpc/touchpad/touchpad.fth \ Touchpad diagnostic
+fload ${BP}/cpu/x86/pc/olpc/copynand.fth
+\ fload ${BP}/cpu/x86/pc/olpc/carousel.fth \ Carouseled NAND writing
+fload ${BP}/cpu/x86/pc/olpc/crypto.fth \ Cryptographic image validation
+fload ${BP}/cpu/x86/pc/olpc/lzip.fth \ Access zip images from memory
+fload ${BP}/cpu/x86/pc/olpc/gamekeys.fth
+fload ${BP}/cpu/x86/pc/olpc/memtest.fth
+
+: emacs ( -- )
+ false to already-go?
+ boot-getline to boot-file " rom:emacs" $boot
+;
+
+fload ${BP}/cpu/x86/pc/rmtools.fth
+fload ${BP}/dev/geode/smi.fth
+fload ${BP}/cpu/x86/pc/olpc/acpi.fth
+fload ${BP}/cpu/x86/pc/olpc/smbios.fth
+\ fload ${BP}/cpu/x86/pc/biosload/rmenter.fth
+fload ${BP}/cpu/x86/pc/biosints.fth
+fload ${BP}/cpu/x86/pc/olpc/biosresume.fth
+
+fload ${BP}/cpu/x86/pc/olpc/setwp.fth
+fload ${BP}/cpu/x86/pc/olpc/security.fth
+fload ${BP}/ofw/gui/ofpong.fth
+fload ${BP}/cpu/x86/pc/olpc/life.fth
+fload ${BP}/cpu/x86/pc/olpc/sound.fth
+[ifdef] wlan-wackup
+fload ${BP}/cpu/x86/pc/olpc/wlantest.fth
+[then]
+fload ${BP}/cpu/x86/pc/olpc/rtcwake.fth
+' gx-power-off to power-off
+[then]
+[then]
+
+[ifdef] Later
+[ifdef] use-ega
+: ega-output ( -- )
+ \ This only works if stdout is currently /display
+ stdout @ if
+ " text-mode3" screen-ih $call-method
+ then
+ " /ega-text" output
+;
+[then]
+[then]
+
+" /xp disk:\boot\olpc.fth sd:\boot\olpc.fth nand:\boot\olpc.fth /prober /usb/ethernet /usb/wlan"
+ ' boot-device set-config-string-default
+
+\needs ramdisk " " d# 128 config-string ramdisk
+" " ' boot-file set-config-string-default \ Let the boot script set the cmdline
+
+[ifdef] Later
+: dimmer ( -- ) screen-ih if " dimmer" screen-ih $call-method then ;
+: brighter ( -- ) screen-ih if " brighter" screen-ih $call-method then ;
+[then]
+
+[ifdef] Later
+dev /8042/keyboard
+0 value waiting-up?
+: olpc-check-abort ( scan-code -- abort? ) \ Square pressed?
+ last-scan over to last-scan ( scan-code old-scan-code )
+ h# e0 <> if drop false exit then ( scan-code )
+
+ check-abort? 0= if drop false exit then ( scan-code )
+
+ dup h# 7f and h# 5d <> if drop false exit then ( scan-code )
+
+ h# 80 and if \ Up
+ false to waiting-up?
+ false ( abort? )
+ else
+ secure? if false else waiting-up? 0= then ( abort? )
+ true to waiting-up?
+ then
+;
+patch olpc-check-abort check-abort get-scan
+
+: handle-volume? ( scan-code -- scan-code flag )
+ dup h# 43 = if dimmer true exit then
+ dup h# 44 = if brighter true exit then
+ dup h# 57 = if softer true exit then
+ dup h# 58 = if louder true exit then
+ false
+;
+' handle-volume? to scan-handled?
+dend
+[then]
+
+\ Eliminate 4 second delay in install console for the case where
+\ there is no keyboard. The delay is unnecessary because the screen
+\ does not go blank when the device is closed.
+patch drop ms install-console
+
+: via-reset-all ( -- )
+[ifdef] Later
+ " screen" " dcon-off" ['] execute-device-method catch if
+ 2drop 2drop
+ then
+
+ ec-reboot \ Tell the EC to reboot us, so the EC can reset too
+[then]
+ 6 h# cf9 pc! \ In case the EC doesn't do it
+ begin halt again
+;
+' via-reset-all to reset-all
+
+alias reboot bye
+
+[ifdef] use-watch-all
+fload ${BP}/cpu/x86/pc/watchall.fth
+[then]
+
+alias crcgen drop ( crc byte -- crc' )
+fload ${BP}/cpu/x86/pc/saveabs.fth
+
+fload ${BP}/forth/lib/selstr.fth
+
+fload ${BP}/ofw/inet/loadtcp.fth
+
+support-package: http
+ fload ${BP}/ofw/inet/http.fth \ HTTP client
+end-support-package
+
+[ifdef] Later
+fload ${BP}/ofw/wifi/wifi-cfg.fth
+support-package: supplicant
+fload ${BP}/ofw/wifi/loadpkg.fth
+end-support-package
+
+: olpc-ssids ( -- $ )
+ " OLPCOFW"nschool-mesh-0"nschool-mesh-1"nschool-mesh-2"
+;
+' olpc-ssids to default-ssids
+
+fload ${BP}/cpu/x86/pc/olpc/nandcastui.fth
+fload ${BP}/cpu/x86/pc/olpc/wifichannel.fth
+fload ${BP}/cpu/x86/pc/olpc/fsupdate.fth
+[then]
+
+fload ${BP}/ofw/inet/sntp.fth
+: olpc-ntp-servers ( -- )
+ " time 172.18.0.1 0.pool.ntp.org 1.pool.ntp.org 2.pool.ntp.org"
+;
+' olpc-ntp-servers to ntp-servers
+: ntp-time&date ( -- s m h d m y )
+ ntp-timestamp abort" Can't contact NTP server"
+ ntp>time&date
+;
+: .clock ( -- )
+ time&date .date space .time ." UTC" cr
+;
+: ntp-set-clock ( -- )
+ ntp-time&date " set-time" clock-node @ $call-method
+ .clock
+;
+
+[ifdef] use-ppp
+fload ${BP}/ofw/ppp/loadppp.fth
+[then]
+
+[ifdef] pc-linux
+" a:\initrd.imz" d# 128 config-string ramdisk
+" root=/dev/ram0 mount_ramdisk=1" ' boot-file set-config-string-default
+" a:\vmlinuz" ' boot-device set-config-string-default
+true ' client-symbols? set-config-int-default
+\ Also try " console=/dev/ttyS0,9600 console=/dev/tty0" in boot-file
+[then]
+
+" dhcp" ' ip-address set-config-string-default
+
+\ fload ${BP}/cpu/x86/pc/report.fth
+fload ${BP}/ofw/core/dualconsole.fth
+
+[ifdef] Later
+: fast-boot? ( -- flag )
+[ifdef] rom-loaded
+ button-x game-key? 0=
+[else]
+ false
+[then]
+;
+[then]
+
+: set-mc ( 19-val 1a-val -- )
+ lbsplit h# 66 h# 69 do i cmos! -1 +loop
+ lbsplit h# 62 h# 65 do i cmos! -1 +loop
+ 1 h# 61 cmos! 1 h# 60 cmos!
+;
+
+: interpreter-init ( -- )
+ hex
+ warning on
+ only forth also definitions
+
+ install-alarm
+
+ page-mode
+ #line off
+
+\ .built cr
+;
+
+[ifdef] Later
+: ?factory-boot-sequence ( -- flag )
+ \ TS is the "test station" tag. Its value is set to "DL" at the
+ \ end of manufacturing test.
+ " TS" find-tag if ( adr len )
+ ?-null " DL" $= 0= ( in-factory? )
+ else ( )
+ \ Missing TS tag is treated as in factory
+ true ( in-factory? )
+ then ( in-factory? )
+ if ( )
+ " /prober /usb/ethernet disk:\boot\olpc.fth nand:\boot\olpc.fth /xp sd:\boot\olpc.fth /usb/wlan"
+ to boot-device
+ then ( )
+;
+[then]
+
+
+[ifdef] Later
+: console-start ( -- )
+[ifdef] rom-loaded
+ video-map cr
+[then]
+ " screen" open-dev ?dup if
+ set-stdout
+\ logo-banner drop
+\ close-dev
+\ 0 stdout !
+ then
+
+ install-dual-console
+
+ ?gui-banner
+\ ." nvramrc" cr
+\ use-nvramrc? if nvramrc safe-evaluate then
+;
+[then]
+: debug-interact ( -- )
+ early-interact? if
+ " Interrupting startup sequence prior to probing" .because
+ ." Type 'resume' to resume normal startup sequence." cr
+ \ fallback-device io console-io
+ ( help-msg ) interact
+ then
+;
+
+[ifdef] Later
+: ?games ( -- )
+ rocker-right game-key? if
+ protect-fw
+ time&date 5drop 1 and if
+ ['] pong guarded
+ else
+ ['] life-demo guarded
+ then
+ power-off
+ then
+;
+: ?diags ( -- )
+ rocker-left game-key? if
+ protect-fw
+ text-on " test-all" ['] eval guarded
+ ." Tests complete - powering off" cr d# 5000 ms power-off
+ then
+;
+
+: ?scan-nand ( -- )
+ rocker-up game-key? if
+ protect-fw text-on ['] scan-nand guarded
+ then
+;
+: ?fs-update ( -- )
+ button-check button-x or button-o or button-square or ( mask )
+ game-key-mask = if protect-fw try-fs-update then
+;
+[then]
+: open-keyboard ( -- )
+ " keyboard" open-dev ?dup if set-stdin then
+;
+
+: startup ( -- )
+ standalone? 0= if exit then
+
+[ifdef] Later
+ block-exceptions
+ no-page
+
+ ?factory-mode
+ ?factory-boot-sequence
+
+ console-start
+
+ board-revision 0= if
+ ." EC problem - disconnect the battery and AC adapter," cr
+ ." reconnect them, and restart." cr
+ begin again
+ then
+
+ read-game-keys
+[then]
+ stdout off \
+
+ " probe-" do-drop-in
+
+ probe-pci
+[ifdef] Later
+ sound
+[then]
+ open-keyboard
+[ifdef] Later
+ ?games
+[then]
+ ['] false to interrupt-auto-boot?
+ probe-usb
+ " probe+" do-drop-in
+
+ interpreter-init
+[ifdef] Later
+ ?scan-nand
+ ?diags
+ ?fs-update
+ secure-startup
+ unblock-exceptions
+[then]
+ ['] (interrupt-auto-boot?) to interrupt-auto-boot?
+ ?usb-keyboard
+[ifdef] Later
+ auto-boot
+[then]
+
+[ifdef] Later
+ frozen? ( frozen? )
+ unfreeze visible ( frozen? )
+ if banner then \ Reissue banner if it was suppressed
+[then]
+
+ blue-letters ." Type 'help' for more information." black-letters
+ cr cr
+
+ quit
+;
+
+: newrom
+ " flash! http:\\10.20.0.14\new.rom" eval
+\ " wifi media lab 802.11" eval
+\ " flash http:\\18.85.46.172\new.rom" eval
+;
+
+[ifdef] use-ec
+\ Fancy battery charge logger.
+fload ${BP}/cpu/x86/pc/olpc/charge.fth
+[then]
+
+\ This helps with TeraTerm, which sends ESC-O as the arrow key prefix
+also hidden also keys-forth definitions
+warning @ warning off
+: esc-o key lastchar ! [""] esc-[ do-command ;
+warning !
+previous previous definitions
+
+tag-file @ fclose tag-file off
+
+.( --- Saving fw.dic ...)
+" fw.dic" $save-forth cr
+
+\ patch foo decimal cold
+
+[ifndef] notdef
+.( --- Saving fw.img ...)
+" fw.img" RAMbase save-abs-rom cr
+[then]
+
+[ifdef] notdef-com32
+.( Saving fw.c32 ...)
+fw-pa h# 10.1000 <> [if]
+.( fw-pa must be 10.1000 for COM32 load format) cr
+[else]
+" fw.c32" RAMbase save-abs-rom cr
+[then]
+[then]
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2006 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/x86/pc/olpc/via/old-reg-settings.fth
===================================================================
--- cpu/x86/pc/olpc/via/old-reg-settings.fth (rev 0)
+++ cpu/x86/pc/olpc/via/old-reg-settings.fth 2009-04-23 08:06:39 UTC (rev 1154)
@@ -0,0 +1,407 @@
+
+[ifdef] old-stuff
+ \ Host bus control device
+ c8 0250 config-wb \ Snoop stall timer
+ \ 251 is set later, after 267
+ ef 0252 config-wb \ CPU Interface ctl Advanced - Enable most speedups
+ 44 0253 config-wb \ Arbitration - occupancy timers
+ 1c 0254 config-wb \ Misc ctl - CPU host Frequency - 100 MHz Host bus 000, 11100 per porting note
+ 24 0255 config-wb \ Misc ctl - 20res, 4+writeRetire
+ 63 0256 config-wb \ Write policy - various knobs
+ 01 0257 config-wb \ HREQ5 calibration - per porting note
+ 09 0259 config-wb \ CPU Misc ctl - 475ns Warm Reset length, also contains Reset bit (8), MSIflat 1
+ 10 025c config-wb \ CPU Misc ctl - MSI redirect
+ a2 025d config-wb \ Write policy 2 - knobs
+ 88 025e config-wb \ Bandwidth timers - knobs
+ ce 025f config-wb \ CPU Misc ctl - knobs
+ \ DRAM timing
+ 2a 0260 config-wb \ DRDY timing ctl for read line 4,3,2,1
+ 00 0261 config-wb \ DRDY timing ctl for read line 8,7,6,5
+ 00 0262 config-wb \ res
+ 15 0263 config-wb \ DRDY timing ctl for read quad 4,3,2,1
+ 00 0264 config-wb \ DRDY timing ctl for read quad 8,7,6,5
+ 00 0265 config-wb \ res
+ 00 0266 config-wb \ DRDY timing ctl for Burst 8-1
+ 00 0267 config-wb \ res
+ f8 0251 config-wb \ 80 bit must be set after 54,55,60-67
+
+ dd 0270 config-wb \ Pullup strengths
+ 66 0271 config-wb \ Pulldown strengths
+ aa 0272 config-wb \ Pullup strengths
+ 55 0273 config-wb \ Pulldown strengths
+\ 30 0274 config-wb \ Reserved
+\ 38 0275 config-wb \ Reserved
+
+ 0c 0276 config-wb \ AGTL+IO config - ROMSIP, 8+ComparatorsOnSuspend
+ 00 027a config-wb \ AGTL Compensation - ROMSIP
+
+ \ The next batch is set by ROMSIP but must be reprogrammed during resume from S3
+ 00 02a0 config-wb
+ 88 02a1 config-wb
+ 56 02a2 config-wb
+ 70 02a3 config-wb
+ 77 02a4 config-wb
+ 77 02a5 config-wb
+ 07 02a6 config-wb
+ 77 02a7 config-wb
+ 77 02a8 config-wb
+ 04 02a9 config-wb
+ 77 02aa config-wb
+ 77 02ab config-wb
+ 77 02ac config-wb
+ 77 02ad config-wb
+ 77 02ae config-wb
+ 77 02af config-wb
+ 77 02b0 config-wb
+ 77 02b1 config-wb
+ 33 02b2 config-wb
+ 33 02b3 config-wb
+ 77 02b4 config-wb
+ 77 02b5 config-wb
+ 77 02b6 config-wb
+ 77 02b7 config-wb
+ 77 02b8 config-wb
+ 77 02b9 config-wb
+ 77 02ba config-wb
+ 77 02bb config-wb
+ 44 02bc config-wb
+ 44 02bd config-wb
+ 14 02be config-wb
+ 75 02c0 config-wb
+ 14 02c1 config-wb
+ 14 02c2 config-wb
+ 10 02c3 config-wb
+ 14 02c4 config-wb
+ 20 02c5 config-wb
+ 14 02c6 config-wb
+ 10 02c7 config-wb
+ 04 02c8 config-wb
+ 10 02c9 config-wb
+ 0b 0290 config-wb \ Misc ctl - DRAM timing
+
+ 0f 03fe config-wb \ 20 bit in this register enables self-refresh
+
+ 4c 0540 config-wb \ res, but called out in S3 resume note
+ 00 0541 config-wb \ res, but called out in S3 resume note
+ 03 0542 config-wb \ res, but called out in S3 resume note
+
+ \ This is the end of the register list that must be restored from ROM code after S3,
+ \ according to the BIOS porting note
+
+ \ DRAM control device
+ 00 0348 config-wb \ Virtual Rank 0 Begin
+ 00 0340 config-wb \ Virtual Rank 0 End
+ 00 0349 config-wb \ Virtual Rank 1 Begin
+ 00 0341 config-wb \ Virtual Rank 1 End
+ 00 034a config-wb \ Virtual Rank 2 Begin
+ 00 0342 config-wb \ Virtual Rank 2 End
+ 00 034b config-wb \ Virtual Rank 3 Begin
+ 08 0343 config-wb \ Virtual Rank 3 End
+
+ \ I think that we write this to send commands to SDRAM - e.g. ee for Init
+ 02 0350 config-wb \ DRAM MA Map Type 1
+
+ 60 0351 config-wb \
+ 11 0352 config-wb \
+ 1f 0353 config-wb \
+
+ \ Need to set 0354 to 89 and 0355 to ab to enable all ranks for probing
+ 00 0354 config-wb \ Physical to Virtual Rank Mapping - DIMM0
+ ab 0355 config-wb \ Physical to Virtual Rank Mapping - DIMM1
+
+ \ 0356,0357 res
+ 00 0358 config-wb \
+ 00 0359 config-wb \
+ 01 035a config-wb \
+ 11 035b config-wb \
+ \ 035c-035f res
+
+ d0 0360 config-wb \ DRAM bus turn-around
+ 55 0361 config-wb \ DRAM timing 1
+ 8a 0362 config-wb \ DRAM timing 2
+ 49 0363 config-wb \ DRAM timing 3
+ 66 0364 config-wb \ DRAM timing 4
+ d1 0365 config-wb \ What?
+ 88 0366 config-wb \ DRAM Arbitration Ctl
+ 00 0367 config-wb \ Command channel select
+ 0c 0368 config-wb \ What?
+ a7 0369 config-wb \ DRAM Page Policy Control
+ 86 036a config-wb \ Refresh Counter
+
+ \ I think we set this to send NOP Commands - see PG_VX855.. section 4.4.2.1
+ 10 036b config-wb \ DRAM Misc ctl
+
+ 8c 036c config-wb \ DRAM Type
+ c0 036d config-wb \ What?
+ 88 036e config-wb \ DRAM Control
+ 42 036f config-wb \
+
+ 00 0370 config-wb \ DQS Output Delay
+ 04 0371 config-wb \ MD Output Delay
+
+ 07 0376 config-wb \ Write Data Phase Control
+ 95 0377 config-wb \ DQS Input Delay for Channel A
+ 83 0378 config-wb \ DQS Input Capture Range
+ 80 0379 config-wb \ res What?
+ 00 037a config-wb \ res What?
+ 20 037b config-wb \ Read Data Phase Control
+ 00 037c config-wb \ Phase Detector Count
+
+ 2a 0380 config-wb \ Page C ROM Shadow
+ 00 0381 config-wb \ Page D ROM Shadow
+ aa 0382 config-wb \ Page E ROM Shadow
+ 20 0383 config-wb \ Page F ROM Shadow
+
+ 00 0384 config-wb \ Low Top Address - Low
+ 20 0385 config-wb \ Low Top Address - High
+
+
+ 3f 0386 config-wb \ SMM and APIC Decoding
+ 0020 0388 config-ww \ Bank End-1
+
+\ 02 038b config-wb \ res
+ 03 038c config-wb \ DQS Output Control
+
+ 04 0390 config-wb \
+ 00 0391 config-wb \
+ 03 0392 config-wb \
+ 04 0393 config-wb \
+\ 00 0394 config-wb \ res
+ 50 0395 config-wb \
+ ac 0396 config-wb \
+ 00 0397 config-wb \
+
+ 00 0398 config-wb \
+ 0c 0399 config-wb \
+\ 00 039a config-wb \ res
+\ 00 039b config-wb \ res
+ b4 039c config-wb \
+\ 00 039d config-wb \ res
+ 91 039e config-wb \
+ 11 039f config-wb \
+
+ ed01 03a0 config-ww \ CPU Direct Access Frame Buffer Ctl
+
+ ee 03a2 config-wb \ Internal GFX Timer
+ 02 03a3 config-wb \ GFX MMIO Base Address1 M1 Space Size
+ 0001 03a4 config-ww \ GFX Misc
+
+ 76 03a6 config-wb \ Page Register Life Timer 1
+ 8c 03a7 config-wb \ GMINT and GFX Related Register
+
+
+\ aa 03b1 config-wb \ res
+ 9a 03b3 config-wb \ GMINTMisc
+
+ 88 03d0 config-wb \
+ 67 03d1 config-wb \
+ 00 03d2 config-wb \
+ 01 03d3 config-wb \
+ 30 03d4 config-wb \
+ 05 03d5 config-wb \
+ fc 03d6 config-wb \
+ 00 03d7 config-wb \
+
+ 80 03db config-wb \
+ 00 03dc config-wb \
+ 00 03dd config-wb \
+
+ 00 03de config-wb \
+ 00 03df config-wb \
+
+ 03e0 9 regs: ee 00 ac 00 44 00 ff 88 86 00
+ 03ec 4 regs: 30 84 00 00
+ 00000000 03f0 config-wl \ DQ/DQS CKG Output Delay Control - Channel A
+ 0000 03f8 config-ww \ DRAM Mode Register Setting Control - Channel B
+
+ 3e 03fb config-wb \ Power Management - Channel A
+
+ a9 03fd config-wb \ Power Management 1
+
+ \ 03fe Already done above
+
+ 3d 03ff config-wb \ The Rest of Registers - DQSB Input Delay, Enable SCMD (MA Bus floats during suspend)
+
+\ After DRAM setup
+
+ 29 037b config-wb
+
+ 1f 00c6 config-wb \ vga-specific - 02+monochromeDisplayAdapter addresses to PCI1
+ \ d0000000 00c8 config-wl \ RO: Graphics memory base address
+ 03 00d4 config-wb \ 2+GfxMemMMIO, 1+GfxMemS.L - Defer to display setup
+ 10 00fe config-wb \ vga-specific - 10+FullDecodeOfVGAports
+
+ 40 0292 config-wb \ Description is rather confusing
+ 00 0293 config-wb \ Description is rather confusing
+
+ 0a 0296 config-wb \ 8+FastTRDR, 2+DynamicHostDataPower
+
+XXX sort of edited to here
+
+ \ 4 Power Management Control
+ db 0484 config-wb \
+ 05 0485 config-wb \
+ f8 0489 config-wb \
+ bf 048b config-wb \
+ 00 048e config-wb \ 20 bit must be set to enter S3
+ 00 048f config-wb \
+ ff 0490 config-wb \
+ ff 0491 config-wb \
+ cc 0492 config-wb \
+ 80 04a0 config-wb \
+ e0 04a1 config-wb \
+ d6 04a2 config-wb \
+ 80 04a3 config-wb \
+ 20 04a8 config-wb \
+
+ \ 5 APIC and Central Traffic Control
+ 18 0580 config-wb \
+
+ \ 6 Scratch
+ \ 7 North-South Module Interface Control
+
+ 02 78c1 config-wb
+ 00 78c6 config-wb \ Note says 4
+ 00 78d5 config-wb
+ 00 78e0 config-wb
+ 02 78e1 config-wb
+
+ 00 8005 config-wb eb 804b config-wb
+ 00 8105 config-wb eb 814b config-wb
+ 00 8205 config-wb eb 824b config-wb
+
+ 20 8441 config-wb
+ 43 8442 config-wb
+ 9e 8448 config-wb
+ 13 844c config-wb
+ 94 844d config-wb
+ 03 844e config-wb
+ 10 844f config-wb \ ?? BPN says 11
+ 80 8450 config-wb
+ 11 8452 config-wb
+ bf 8453 config-wb
+ 0b 8459 config-wb
+ cc 845a config-wb
+ cc 845b config-wb \ ?? BPN says 44
+ 00 845c config-wb
+ cc 845d config-wb
+
+ \ Dev 17 Fun 0
+ 44 8840 config-wb
+ f0 8842 config-wb
+ 00 8844 config-wb
+ 00 8845 config-wb
+ 00 8846 config-wb
+ 00 8848 config-wb
+ 01 884d config-wb
+ c0 8850 config-wb \ 40 disables USB device mode, 80 is reserved!!
+ 4d 8851 config-wb \ 40 is reserved, 8+RTC, 4+MSE, 1+KBD
+ 19 8852 config-wb \ Serial IRQ control
+ 80 8853 config-wb \ PC/PCI DMA control 80+DMA
+ 00 8854 config-wb \ PCI INT inversion; default is okay
+ a0 8855 config-wb \ PCI PnP Interrupt routing 1 INTA#,GPIO14 - INTA# -> IRQ10
+ b9 8856 config-wb \ PCI PnP Interrupt routing 2 INTC#,INTB#
+ a0 8857 config-wb \ PCI PnP Interrupt routing 3 INTD#,reserved
+ 60 8858 config-wb \ South module misc - 40+APIC, 20+33MhzInts, 2 write protects RTC 0xD ?? 62
+ 00 8859 config-wb \ South module misc
+ 53 885b config-wb \ misc 40-port80onLPC, 10+DMAoutToPCI, 2reserved,1+dynamicClockStop
+
+ 80 8868 config-wb \ HPET - 80+HPET
+ 00 8869 config-wb \ HPET base 15:8
+ d0 886a config-wb \ HPET base 23:15
+ fe 886b config-wb \ HPET base 31:24 - fed0.0000
+
+ 00 886c config-wb \ ISA pos decode - OBIO, MSS, APIC, ROM, PCS1#, PCS0#
+ 00 886d config-wb \ ISA pos decode - FDC, LPT, Game, MIDI
+ df 886e config-wb \ ISA pos decode - FDC, LPT, Game, MIDI
+ 00 886f config-wb \ ISA pos decode - SPI, TPM, PCS2/3, CF9, FDC, SoundBlaster
+
+ 1106 8870 config-ww \ Subsystem vendor ID backdoor 2D-2C
+ 3337 8872 config-ww \ Subsystem vendor ID backdoor 2F-2E
+
+ \ 8875-887f LPC and firmware memory IDSELs
+ 20 8880 config-wb \ 20+DebouncePwrBtn
+ 84 8881 config-wb \ 80+ACPIIO, 4+GuardRTCduringPowerTransitions
+ 50 8882 config-wb \ 50isRO, low 4 bits select APCI IRQ - 0 is disabled
+ 40da 8884 config-ww \ Primary interrupt channels mask - 14,7,c,4,3,1
+ 0000 8886 config-ww \ Secondary interrupt channels mask
+ 4001 8888 config-ww \ ACPI Power Management I/O base - Ports 4000+
+ 1f 888a config-wb \ Auto-switch power state
+ 07 888c config-wb \ Host Power Management Control - thermal throttling off
+ 18 888d config-wb \ Throttle/ClockStopControl
+\ 0020e800 8890 config-wl \ Power Management Timer Control - throttling off, timers disabled
+ 28 8894 config-wb \ Power well - 20+StopNorthInS1, 8+SDIOpowerSwitchPullup
+ c1 8895 config-wb \ Power well - 80+FastResume, 40+StartNorthPLLbeforePWRGDonS4resume, 1+USBwake
+ 08 8896 config-wb \ Battery well - 8=CPUfreqStrapValue
+ 80 8897 config-wb \ Power well - 80+WaitForPWRGDlowBeforeWake
+ 00 8898 config-wb \ GP2/GP3 timer control - I think GP3 is a BIOS watchdog
+ 88 889b config-wb \ Boot option mask - 80reserved, 8+USBwake
+ ad 889f config-wb \ SDIO change - 80+KB/MSpullup, 20reserved, 08+10msSDIOpowerUpDelay, 4useCRforSDMMC,1unmaskINTRbefore8259init
+ 00 88b0 config-wb \ UART enables and APIC C4 state control
+\ 34 88b2 config-wb \ UART IRQ routing
+\ 00 88b4 config-wb \ UART1 base address
+\ 00 88b5 config-wb \ UART2 base address
+ 40 88b7 config-wb \ COM control - 40reserved
+\ 00 88b8 config-wb \ UART DMA base low
+\ 00 88b9 config-wb \ UART DMA base high
+ 00 88ba config-wb \ UART1 DMA Channel Control
+ 00 88bb config-wb \ UART2 DMA Channel Control
+ d3 88bd config-wb \ SPI MMIO base address 15:8
+ fe 88be config-wb \ SPI MMIO base address 23:16
+ 90 88bf config-wb \ SPI MMIO base address 31:24 - 90fe.d300
+ 4101 88d0 config-ww \ SMBus I/O base address - Port 4100
+ 01 88d2 config-wb \ SMBus host config - 1+SMBusHostCtlr
+ eb 88e2 config-wb \ Internal NorthPLL Ctl - 80+InhibitC4inUSBisochronous, rest reserved
+ 03 88e3 config-wb \ pullups, break events
+ a0 88e4 config-wb \ multi-function select 1 - 80+FastC3/4, 20+GPO5/6
+ 60 88e5 config-wb \ multi-function select 2 - 40+NorthBusMaster, 20+NorthIntWakesCx
+ 20 88e6 config-wb \ Break event enable 1 - 20+PCIbusMasterBreakEvent
+ 80 88e7 config-wb \ Break event enable 2 - 80+APICcycleReflect
+ 00 88ec config-wb \ Watchdog off
+ 04 88fc config-wb \ Processor control - 4:DPSLP#toSLP#latencyInRange7.5-15uS
+
+ \ Dev 17 Fun 7
+ 43 8f4f config-wb \ North/South interface ctl - 40+enableExtPCI,2+ExtendedConfigSpace,1+ReadFlushesWrFIFO
+ 08 8f50 config-wb \ Priorities - 8+HDACHighPriority
+ 80 8f51 config-wb \ P2P Bridge - 80+SubtractiveDecode (but doc says 1 should be set too)
+ 11 8f52 config-wb \ Fast timeouts for SM and HDAC Occupy
+ 11 8f53 config-wb \ Fast timeouts for SM and HDAC Promotes
+ 02 8f54 config-wb \ Synchronize requests - 2+SyncUSBreq
+
+ 80 8f60 config-wb \ DRAM Bank 7 End high 8 bits
+ 2a 8f61 config-wb \ Page C ROM Shadow ctl - cc000 disabled, c0000-cbfff RO
+ 00 8f62 config-wb \ Page D ROM Shadow ctl - c0000-cffff disabled
+ a0 8f63 config-wb \ Page E and F Shadow ctl - e0000-fffff RO, no hole - this might be for SMI
+ aa 8f64 config-wb \ Page E ROM Shadow ctl - e0000-effff RO
+
+ 82 8f70 config-wb \ CPU to PCI Flow ctl 1 - 80+PostedWrites,2+DelayTransaction
+ c8 8f71 config-wb \ CPU to PCI Flow ctl 2 - 80isRW1C, 40+FiniteRetries, 8+BurstTimeout
+ ee 8f72 config-wb \ P2C cache ctl - various
+ 01 8f73 config-wb \ PCI Master ctl - 1+BrokenMasterTimer
+ 0c 8f74 config-wb \ South/North interface ctl - complicated
+ 0f 8f75 config-wb \ PCI arb 1 - 8 disable master bus timeout
+ 50 8f76 config-wb \ PCI arb 2 - 40+Parking, 10+CPUgetsEveryThirdcycle
+ 48 8f77 config-wb \ South misc - DMA write doesn't block PIO read, 1 ms read timeout
+ 02 8f7c config-wb \ 2+APIC FSB bypasses PCI
+
+ 07 8f80 config-wb \ disable read-around-write for PCI1,HDAC,APIC
+ 21 8f82 config-wb \ CCA test mode thing
+
+ 00 8fd1 config-wb \ 0 in 04 bit enables HDAC
+ 93 8fe0 config-wb \ Dynamic clock control 1
+\ 08 8fe1 config-wb \ reserved
+ 00 8fe2 config-wb \ Dynamic clock control 3 - use dynamic clocking
+
+ 5e 8fe3 config-wb \ various PCI things
+
+ 80 8fe5 config-wb \ DRAM low top address bits 31:24
+ 3f 8fe6 config-wb \ SMM/APIC Decoding - some SMM addresses to PCI2, MSI snoop, 4+TopSMM,2+HighSMM,1+CompatSMM
+
+ 48 8ffc config-wb \ PCI Bus ctl - 40+CCAreadClk 8res
+
+
+ 07 26 pmio-wb \ PMIO processor ctl
+\ PMIO 2b xxxxxx1x \ 2+THRMTRIP#
+\ PMIO 66 xxxxxx1x \ 2+P61FisSTPGNT
+[then]
+
Added: cpu/x86/pc/olpc/via/olpc.bth
===================================================================
--- cpu/x86/pc/olpc/via/olpc.bth (rev 0)
+++ cpu/x86/pc/olpc/via/olpc.bth 2009-04-23 08:06:39 UTC (rev 1154)
@@ -0,0 +1,197 @@
+purpose: Construct the Open Firmware module collection
+
+command: &builder &this
+in: ${BP}/cpu/x86/pc/olpc/via/build/ec.img
+in: ${BP}/cpu/x86/pc/olpc/via/build/romreset.di
+in: ${BP}/cpu/x86/pc/olpc/via/build/resume.di
+in: ${BP}/cpu/x86/pc/olpc/via/build/rmstart.img
+in: ${BP}/cpu/x86/pc/olpc/via/build/paging.di
+in: ${BP}/cpu/x86/pc/olpc/via/build/fw.dic
+in: ${BP}/dev/mmc/sdhci/build/sdhci.fc
+in: ${BP}/dev/mmc/sdhci/build/sdmmc.fc
+in: ${BP}/dev/usb2/hcd/ohci/build/ohci.fc
+in: ${BP}/dev/usb2/hcd/ehci/build/ehci.fc
+in: ${BP}/dev/usb2/device/hub/build/hub.fc
+in: ${BP}/dev/usb2/device/generic/build/generic.fc
+in: ${BP}/dev/usb2/device/net/build/usbnet.fc
+in: ${BP}/dev/usb2/device/serial/build/usbserial.fc
+in: ${BP}/dev/usb2/device/storage/build/usbstorage.fc
+in: ${BP}/dev/usb2/device/keyboard/build/usbkbd.fc
+in: ${BP}/clients/memtest86/memtest
+in: ${BP}/clients/emacs/x86/emacs
+in: ${BP}/cpu/x86/pc/olpc/via/build/verify.img
+in: ${BP}/dev/pci/build/pcibridg.fc
+\ in: ${BP}/cpu/x86/pc/olpc/via/build/camera.fc
+\ VIA-PATA
+\ in: ${BP}/cpu/x86/pc/olpc/via/build/dsdt.aml
+\ in: ${BP}/cpu/x86/pc/olpc/via/build/mcastnand.bin
+\ in: ${BP}/dev/hdaudio/build/hdaudio.fc
+
+build-now
+
+fload ${BP}/cpu/x86/pc/olpc/via/versions.fth
+
+" macro: FW_VERSION Q3${FW_MAJOR}${FW_MINOR}" expand$ eval
+
+fload ${BP}/cpu/x86/pc/olpc/via/config.fth
+
+\ Always re-create the builton.fth file when we make a new rom.img
+fload ${BP}/cpu/x86/pc/builton.bth
+fload ${BP}/cpu/x86/pc/olpc/via/sourceurl.fth
+
+fload ${BP}/forth/lib/crc32.fth
+
+hex
+
+: pad-file ( location -- )
+ ofd @ fsize
+ 2dup u< abort" The ROM image is too large"
+ ?do h# ff ofd @ fputc loop
+;
+
+.( --- Saving as )
+" ${FW_VERSION}.rom" expand$ 2dup lower ( adr len )
+2dup type cr ( adr len )
+$new-file
+[ifdef] Later
+ " ec.img" $add-file
+[then]
+
+ dropin-base rom-pa - pad-file
+
+ " romreset.di" $add-file
+\ " romstart.di" $add-file
+
+[ifdef] Later
+ " resume.di" $add-file
+[then]
+
+[ifndef] Later
+\ Loads the set of drivers that is common to different output formats
+
+\ " paging.di" $add-file
+ " ${BP}/cpu/x86/build/inflate.bin" " inflate" $add-dropin
+ " fw.img" " firmware" $add-deflated-dropin
+[then]
+
+ " ${BP}/dev/usb2/hcd/ohci/build/ohci.fc" " class0c0310" $add-deflated-dropin
+ " ${BP}/dev/usb2/hcd/ehci/build/ehci.fc" " class0c0320" $add-deflated-dropin
+ " ${BP}/dev/usb2/device/hub/build/hub.fc" " usb,class9" $add-dropin
+ " ${BP}/dev/usb2/device/generic/build/generic.fc" " usbdevice" $add-deflated-dropin
+ " ${BP}/dev/usb2/device/net/build/usbnet.fc" " usbnet" $add-deflated-dropin
+ " ${BP}/dev/usb2/device/keyboard/build/usbkbd.fc" " usb,class3,1" $add-dropin
+ " ${BP}/dev/usb2/device/serial/build/usbserial.fc" " usbserial" $add-deflated-dropin
+ " ${BP}/dev/usb2/device/storage/build/usbstorage.fc" " usbstorage" $add-deflated-dropin
+\ " mrv8686.bin" " mrv8686.bin" $add-deflated-dropin
+
+ " ${BP}/dev/mmc/sdhci/build/sdhci.fc" " class080501" $add-deflated-dropin
+ " ${BP}/dev/mmc/sdhci/build/sdmmc.fc" " sdmmc" $add-deflated-dropin
+ " builton.fth" " probe-" $add-dropin
+
+ " ${BP}/clients/emacs/x86/emacs" " emacs" $add-deflated-dropin
+ " ${BP}/clients/emacs/x86/emacs.rc" " emacs.rc" $add-deflated-dropin
+ " ${BP}/clients/emacs/emacs.hlp" " emacs.hlp" $add-deflated-dropin
+
+[ifdef] Later
+ " ${BP}/dev/hdaudio/build/hdaudio.fc" " class040300" $add-deflated-dropin
+
+ " ${BP}/ofw/fcode/memtest.fth" " memtest.fth" $add-deflated-dropin
+
+ " ${BP}/ofw/inet/telnetd.fth" " telnetd" $add-deflated-dropin
+
+\ " ${BP}/cpu/x86/pc/olpc/images/warnings.565" " warnings.565" $add-deflated-dropin
+ " ${BP}/cpu/x86/pc/olpc/images/lightdot.565" " lightdot.565" $add-deflated-dropin
+ " ${BP}/cpu/x86/pc/olpc/images/yellowdot.565" " yellowdot.565" $add-deflated-dropin
+ " ${BP}/cpu/x86/pc/olpc/images/darkdot.565" " darkdot.565" $add-deflated-dropin
+ " ${BP}/cpu/x86/pc/olpc/images/lock.565" " lock.565" $add-deflated-dropin
+ " ${BP}/cpu/x86/pc/olpc/images/unlock.565" " unlock.565" $add-deflated-dropin
+ " ${BP}/cpu/x86/pc/olpc/images/plus.565" " plus.565" $add-deflated-dropin
+ " ${BP}/cpu/x86/pc/olpc/images/minus.565" " minus.565" $add-deflated-dropin
+ " ${BP}/cpu/x86/pc/olpc/images/x.565" " x.565" $add-deflated-dropin
+ " ${BP}/cpu/x86/pc/olpc/images/sad.565" " sad.565" $add-deflated-dropin
+ " ${BP}/cpu/x86/pc/olpc/images/bigdot.565" " bigdot.565" $add-deflated-dropin
+
+ " ${BP}/cpu/x86/pc/olpc/images/check.565" " check.565" $add-deflated-dropin
+ " ${BP}/cpu/x86/pc/olpc/images/xogray.565" " xogray.565" $add-deflated-dropin
+ " ${BP}/cpu/x86/pc/olpc/images/laptop.565" " nand.565" $add-deflated-dropin
+ " ${BP}/cpu/x86/pc/olpc/images/laptop.565" " fastnand.565" $add-deflated-dropin
+ " ${BP}/cpu/x86/pc/olpc/images/ethernet.565" " ethernet.565" $add-deflated-dropin
+ " ${BP}/cpu/x86/pc/olpc/images/usbkey.565" " disk.565" $add-deflated-dropin
+ " ${BP}/cpu/x86/pc/olpc/images/wireless.565" " wlan.565" $add-deflated-dropin
+ " ${BP}/cpu/x86/pc/olpc/images/xo.565" " xo.565" $add-deflated-dropin
+ " ${BP}/cpu/x86/pc/olpc/images/sd.565" " sd.565" $add-deflated-dropin
+[then]
+
+ " ${BP}/ofw/termemu/15x30pc.psf" " font" $add-deflated-dropin
+[ifdef] use-ega
+ " ${BP}/ofw/termemu/cp881-16.obf" " pcfont" $add-deflated-dropin
+[then]
+
+[ifdef] Later
+ " verify.img" " verify" $add-deflated-dropin
+ " os.public" " ospubkey" $add-dropin \ Incompressible
+ " fw.public" " fwpubkey" $add-dropin \ Incompressible
+ " fs.public" " fspubkey" $add-dropin \ Incompressible
+ " lease.public" " leasepubkey" $add-dropin \ Incompressible
+ " developer.public" " develpubkey" $add-dropin \ Incompressible
+
+ " sourceurl" " sourceurl" $add-dropin
+
+ " ${BP}/clients/memtest86/memtest" " memtest" $add-deflated-dropin
+ " ${BP}/cpu/x86/pc/olpc/images/Edge1-8k-EQ-Comp-Amp-Short.wav" " splash" $add-deflated-dropin
+ " ${BP}/cpu/x86/pc/olpc/via/build/dsdt.aml" " dsdt" $add-deflated-dropin
+\ " ${BP}/cpu/x86/pc/olpc/via/build/ssdt.aml" " ssdt" $add-deflated-dropin
+
+ " ${BP}/cpu/x86/pc/olpc/via/build/nandblaster_rx.bin" " nb_rx" $add-deflated-dropin
+ " ${BP}/cpu/x86/pc/olpc/via/build/nandblaster_tx.bin" " nb_tx" $add-deflated-dropin
+[then]
+
+ /rom h# 400 - pad-file \ rmstart image must start 0x400 from end
+ " rmstart.img" $add-file
+
+\ Insert the revision signature
+/rom h# 40 - ofd @ fseek
+h# 10 buffer: signature
+signature h# 10 blank
+" CL1" signature swap move
+" ${FW_VERSION}" expand$ signature 6 + swap move
+" Q3${FW_MAJOR}" expand$ signature d# 13 + swap move
+signature h# 10 ofd @ fputs
+
+create sipbuf
+ cc c, 66 c, aa c, 55 c, 54 c, 24 c, 01 c, 88 c,
+ 77 c, 77 c, 10 c, 77 c, 14 c, 08 c, 77 c, 00 c,
+ 00 c, 00 c, 00 c, 00 c, 00 c, 00 c, 00 c, 00 c,
+ 00 c, 00 c, 00 c, 00 c, 00 c, 00 c, 00 c, 00 c,
+here sipbuf - constant /sipbuf
+
+/l buffer: crcbuf
+/rom buffer: filebuf
+0 ofd @ fseek
+
+\ Read the entire image, compute the CRC, and store it h# 30 from the end
+filebuf /rom ofd @ fgets /rom <> abort" Can't read back image"
+0 crctab filebuf /rom ($crc) crcbuf !
+
+/rom h# 2c - ofd @ fseek
+crcbuf /l ofd @ fputs
+
+\ Via SIP ROM pointer
+\ The address "-30" is fixed by the VX855 hardware.
+\ We get to choose the address ffffffa0
+h# ffffff80 crcbuf l!
+/rom h# 30 - ofd @ fseek
+crcbuf /l ofd @ fputs
+
+/rom h# 80 - ofd @ fseek
+sipbuf /sipbuf ofd @ fputs
+
+ofd @ fclose
+
+\ Creating olpc.version serves two purposes:
+\ a) It reports the firmware revision for use by external scripts
+\ b) It provides an olpc.* artifact for the builder dependency management.
+
+writing olpc.version
+" ${FW_VERSION}" expand$ 2dup lower ofd @ fputs
+ofd @ fclose
Added: cpu/x86/pc/olpc/via/pcinode.fth
===================================================================
--- cpu/x86/pc/olpc/via/pcinode.fth (rev 0)
+++ cpu/x86/pc/olpc/via/pcinode.fth 2009-04-23 08:06:39 UTC (rev 1154)
@@ -0,0 +1,176 @@
+\ See license at end of file
+purpose: PCI bus package
+
+: preassigned-pci-slot? ( my-space -- flag )
+ h# f.f800 and
+ dup h# 800 = if drop true exit then
+ drop false
+;
+
+0 [if]
+ \ Suppress PCI address assignment; use the addresses the BIOS assigned
+ patch false true master-probe
+ patch noop assign-all-addresses prober
+ patch noop clear-addresses populate-device-node
+ patch noop clear-addresses populate-device-node
+ patch noop temp-assign-addresses find-fcode?
+ patch 2drop my-w! populate-device-node
+ : or-w! ( bitmask reg# -- ) tuck my-w@ or swap my-w! ;
+ patch or-w! my-w! find-fcode?
+ patch 2drop my-w! find-fcode?
+[then]
+
+[ifdef] addresses-assigned
+\ patch false true master-probe
+: nonvirtual-probe-state? ( -- flag )
+ my-space preassigned-pci-slot? if false else probe-state? then
+;
+patch nonvirtual-probe-state? probe-state? map-in
+
+\ patch noop assign-all-addresses prober
+warning @ warning off
+: assign-pci-addr ( phys.lo phys.mid phys.hi len | -1 -- phys.hi paddr size )
+ 2dup -1 <> swap preassigned-pci-slot? and if ( phys.lo phys.mid phys.hi len )
+ 2swap 2drop >r ( phys.hi r: len )
+ dup config-l@ 1 invert and r> ( phys.hi paddr len )
+ exit
+ then
+ assign-pci-addr
+;
+warning !
+
+: ?clear-addresses ( -- )
+ my-space preassigned-pci-slot? if exit then clear-addresses
+;
+patch ?clear-addresses clear-addresses populate-device-node
+patch ?clear-addresses clear-addresses populate-device-node
+
+: ?temp-assign-addresses ( -- )
+ my-space preassigned-pci-slot? if exit then temp-assign-addresses
+;
+
+patch ?temp-assign-addresses temp-assign-addresses find-fcode?
+
+\ These patches leave devices turned on
+\ patch 2drop my-w! populate-device-node
+\ : or-w! ( bitmask reg# -- ) tuck my-w@ or swap my-w! ;
+\ patch or-w! my-w! find-fcode?
+\ patch 2drop my-w! find-fcode?
+[then]
+
+h# 0000 encode-int " slave-only" property
+h# 0000 encode-int \ Mask of implemented add-in slots
+" slot-names" property
+
+also forth definitions
+
+: pci-probe-list ( -- adr len )
+ " 1,c,f,10,13,14"
+;
+\ " c,f" dup config-string pci-probe-list
+
+previous definitions
+
+h# b000.0000 to first-mem
+h# c000.0000 to mem-space-top
+h# 0000.8000 to first-io \ Avoid mappings established by BIOS
+
+0 [if]
+\ These are here for completeness, but won't be used because we don't
+\ do dynamic address assignment on this system.
+h# 1000.0000 to first-mem \ Avoid RAM at low addresses
+h# 2000.0000 to mem-space-top
+h# 0000.8000 to first-io \ Avoid mappings established by BIOS
+[then]
+
+\ Determine the parent interrupt information (the "interrupt line" in PCI
+\ parlance) from the child's "interrupt pin" and the child's address,
+\ returning "int-line true" if the child's interrupt line register should
+\ be set or "false" otherwise.
+: assign-int-line ( phys.hi.func INTx -- irq true )
+ \ Reiterate the value that is already in the int line register,
+ \ which was placed there by lower level init code
+ drop h# 3c + config-b@ true
+;
+
+0 value interrupt-parent
+
+1 " #interrupt-cells" integer-property
+0 0 encode-bytes 0000.ff00 +i 0+i 0+i 7 +i " interrupt-map-mask" property
+
+: +map ( adr len dev# int-pin# int-level -- adr' len' )
+ >r >r ( $ dev# R: level pin )
+ +i ( $' R: level pin )
+ 0+i 0+i r> +i ( $' R: level )
+ interrupt-parent +i ( $' R: level )
+ r> +i 0 +i ( $' ) \ 0 is active low, level senstive for ISA
+;
+
+external
+
+: make-interrupt-map ( -- )
+ " /isa/interrupt-controller" find-package 0= if exit then to interrupt-parent
+
+ 0 0 encode-bytes ( prop$ )
+
+ h# 10000 0 do ( prop$ )
+ i h# 3d + config-b@ ( prop$ pin# )
+ dup 0<> over h# ff <> and if ( prop$ pin# )
+ i h# 3c + config-b@ ( prop$ pin# level )
+ i -rot +map ( prop$' )
+ else ( prop$ pin# )
+ drop ( prop$ )
+ then ( prop$ )
+ h# 100 +loop ( prop$ )
+ " interrupt-map" property ( )
+;
+
+also known-int-properties definitions
+\ In some systems the number of interrupt-map ints is variable,
+\ but on OLPC, the only node with an interrupt-map is PCI.
+: interrupt-map 7 ;
+: interrupt-map-mask 4 ;
+previous definitions
+
+\ Just use the global versions
+warning @ warning off
+: config-b@ ( config-adr -- b ) config-b@ ;
+: config-w@ ( config-adr -- w ) config-w@ ;
+: config-l@ ( config-adr -- l ) config-l@ ;
+: config-b! ( b config-adr -- ) config-b! ;
+: config-w! ( w config-adr -- ) config-w! ;
+: config-l! ( l config-adr -- ) config-l! ;
+warning !
+
+\ The io-base handling really ought to be in the root node, but
+\ that would require more changes than I'm willing to do at present.
+warning @ warning off
+: map-out ( vaddr size -- )
+ over io-base u>= if 2drop exit then ( vaddr size )
+ map-out ( )
+;
+warning !
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2006 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/x86/pc/olpc/via/probemem.fth
===================================================================
--- cpu/x86/pc/olpc/via/probemem.fth (rev 0)
+++ cpu/x86/pc/olpc/via/probemem.fth 2009-04-23 08:06:39 UTC (rev 1154)
@@ -0,0 +1,129 @@
+\ See license at end of file
+purpose: Create memory node properties and lists
+
+\ All RAM, including that assigned to the frame buffer
+: total-ram ( -- ramsize )
+ \ Search for the last "top of rank" value
+ h# 340 h# 343 do
+ i config-b@ ?dup if ( chunks ) \ Each chunk is 64 MiB
+ d# 26 lshift ( bytes )
+ unloop exit
+ then
+ -1 +loop
+ ." Can't get total RAM size!" cr
+ h# 1000.0000
+;
+
+\ Offset of frame buffer/display memory within the memory array
+: fb-offset ( -- offset ) mem-info-pa 4 + l@ ;
+
+\ Excludes RAM assigned to the frame buffer
+: system-ram ( -- extant avail )
+ fb-offset
+;
+
+\ This may require adjustment if we steal additional SMI memory
+: fbsize ( -- ) total-ram fb-offset - ;
+
+dev /memory
+
+\ Excludes RAM already used for page tables
+: ram-limit ( -- addr ) mem-info-pa la1+ l@ ;
+
+: release-range ( start-adr end-adr -- ) over - release ;
+
+: probe ( -- )
+[ifdef] relocated-fw
+ system-ram /fw-area - to fw-pa
+[then]
+
+ 0 total-ram reg \ Report extant memory
+
+ \ Put h# 10.0000-1f.ffff and 28.0000-memsize in pool,
+ \ reserving 0..10.0000 for the firmware
+ \ and 20.0000-27.ffff for the "flash"
+
+\ h# 0.0000 h# 02.0000 release \ A little bit of DMA space, we hope
+\ h# 10.0000 h# 0f.ffff release
+\ h# 28.0000 h# 80.0000 release-range
+
+\ Release some of the first meg, between the page tables and the DOS hole,
+\ for use as DMA memory.
+ mem-info-pa 2 la+ l@ h# a.0000 release-range \ Below DOS hole
+
+[ifdef] virtual-mode
+ \ Release from 1M up to the amount of unallocated (so far) memory
+ dropin-base ram-limit u< if
+ \ Except for the area that contains the dropins, if they are in RAM
+ h# 10.0000 dropin-base release-range
+ dropin-base dropin-size + ram-limit release-range
+ else
+ h# 10.0000 ram-limit release-range
+ then
+[else]
+ h# 10.0000 system-ram release-range
+
+ fw-pa /fw-ram 0 claim drop
+
+ \ Account for the dropin area if it is in RAM
+ dropin-base system-ram u< if
+ dropin-base dropin-size 0 claim
+ then
+
+[ifdef] relocated-fw
+ initial-heap swap >physical swap 0 claim drop
+[else]
+ initial-heap 0 claim drop
+[then]
+[then]
+;
+
+[ifndef] 8u.h
+: 8u.h ( n -- ) push-hex (.8) type pop-base ;
+[then]
+: .chunk ( adr len -- ) ." Testing memory at: " swap 8u.h ." size " 8u.h cr ;
+: selftest ( -- error? )
+ " available" get-my-property if ." No available property" cr true exit then
+ ( adr len )
+ begin ?dup while
+ 2 decode-ints swap ( rem$ chunk$ )
+ 2dup .chunk ( rem$ chunk$ )
+[ifdef] virtual-mode
+ 2dup over swap 3 mmu-map ( rem$ chunk$ )
+[then]
+ memory-test-suite if 2drop true exit then ( rem$ )
+ repeat drop
+ false
+;
+
+device-end
+
+also forth definitions
+stand-init: Probing memory
+ " probe" memory-node @ $call-method
+;
+previous definitions
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2006 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/x86/pc/olpc/via/rmstart.bth
===================================================================
--- cpu/x86/pc/olpc/via/rmstart.bth (rev 0)
+++ cpu/x86/pc/olpc/via/rmstart.bth 2009-04-23 08:06:39 UTC (rev 1154)
@@ -0,0 +1,10 @@
+\ See license at end of file
+purpose: Build script fo x86 real mode startup code.
+
+command: &builder &this
+build-now
+
+\ create debug-reset
+
+fload ${BP}/cpu/x86/pc/olpc/via/config.fth
+fload ${BP}/cpu/x86/pc/olpc/via/rmstart.fth
Added: cpu/x86/pc/olpc/via/rmstart.fth
===================================================================
--- cpu/x86/pc/olpc/via/rmstart.fth (rev 0)
+++ cpu/x86/pc/olpc/via/rmstart.fth 2009-04-23 08:06:39 UTC (rev 1154)
@@ -0,0 +1,238 @@
+\ See license at end of file
+purpose: x86 real mode startup code.
+
+command: &native &this
+build-now
+
+\ 386/486 processors begin executing at address ffff.fff0 in real mode
+\ when they come out of reset. Normally, that address would not be
+\ accessable in real mode, but the processor does some magic things to
+\ the Code Segment register so that the high order address lines are
+\ "boosted" up to the ffff.xxxx range just after reset. The "boosting"
+\ persists until the CS register is modified (i.e. with a far jump).
+
+\ The other segment register are not "boosted", so they can only access
+\ the normal real mode range, essentially just the first megabyte.
+
+\ The startup code must establish a Global Descriptor Table containing
+\ suitable mappings, and then enter protected mode. The space between
+\ ffff.fff0 and the end of the ROM is insufficient to do this, so the
+\ first few instructions must jump elsewhere, to a place where there
+\ is enough room.
+
+\ The code below is rather tricky, especially since the Forth assembler
+\ always assumes 32-bit operand size and 32-bit addressing modes.
+\ The code is executing in 16-bit mode, so the assembler must be used
+\ carefully to ensure generation of the correct opcodes, and override
+\ prefixes where necessary.
+
+
+\needs start-assembling fload ${BP}/cpu/x86/asmtools.fth
+\needs write-dropin fload ${BP}/forth/lib/mkdropin.fth
+fload ${BP}/cpu/x86/pc/port80.fth
+
+hex
+
+start-assembling
+hex
+
+\ Addresses where the following items will be located in the processor's
+\ physical address space:
+
+\ ffff.fc00: GDT ( 3 entries ) + padding
+\ ffff.fc20: GDT address + size ( 6 bytes ) plus padding
+\ ffff.fc28: Startup code plus padding
+\ ffff.fff0: Reset entry point - jump to startup code plus padding to end
+
+\ Assembler macros for startup diagnostics
+
+\ write a byte to an ISA port
+: risa-c! ( n a - ) " # dx mov # al mov al dx out " evaluate ;
+
+: num>asc ( al: b -- al: low ah: hi )
+ " al ah mov " evaluate
+ " h# f # al and " evaluate
+ " h# 9 # al cmp > if h# 57 # al add else h# 30 # al add then " evaluate
+
+ " ah shr ah shr ah shr ah shr " evaluate \ shift down four bits
+ " h# f # ah and " evaluate
+ " h# 9 # ah cmp > if h# 57 # ah add else h# 30 # ah add then " evaluate
+
+ " al bl mov ah al mov bl ah mov " evaluate
+;
+
+[ifdef] debug-reset
+[else]
+: report ( char -- ) drop ;
+: reportc ( -- ) ;
+[then]
+
+hex
+
+\ odds for testing, evens for release
+d# 8 constant loader-version# \ monotonic
+2 constant loader-format# \ >1 when crc present
+
+.( ROM loader: version# ) loader-version# .d
+.( , format# ) loader-format# .d cr
+
+\ Real Mode Startup
+
+hex
+
+label rm-startup \ Executes in real mode with 16-bit operand forms
+
+ \ ffff.fc00 GDT
+
+ 0 w, 0 l, 0 w, \ 0 Mandatory null descriptor
+ 0 w, 0 l, 0 w, \ * Another null descriptor
+ ffff w, 9b.000000 l, 00.c.f w, \ 10 Code, linear=physical, full 4Gbytes
+ ffff w, 93.000000 l, 00.c.f w, \ 18 Data, linear=physical, full 4Gbytes
+
+ \ ffff.fc20 GDT limit + address
+
+ 1f w, ffff.fc00 l, \ # slots (4 * 8 - 1) , starting address
+ 0 w, \ Padding
+
+ \ ------->>>>> Startup code, reached by branch from main entry point below
+ \
+ \ ffff.fc28
+
+ here \ Mark the beginning of this code so its size may be determined
+ \ and so that a jump to it may be assembled later.
+
+ 16-bit
+
+ \ PLL startup?
+
+ \ Return to here after the reset
+ h# 02 port80
+
+ \ Invalidate TLB
+ op: ax ax xor
+ op: ax cr3 mov
+
+[ifdef] init-com1 init-com1 [then]
+
+[ifdef] debug-reset
+carret report \ send it to com1 if you can...
+linefeed report \ send it to com1 if you can...
+ascii F report \ send it to com1 if you can...
+[then]
+
+ \ The following instruction uses the CS: segment override because
+ \ that segment is currently "boosted" up into the ROM space.
+ \ It uses the operation size override to load a 32-bit pointer.
+ \ The address override is not used; the GDT limit/address data structure
+ \ above is reachable with a 16-bit address and through the "boosted"
+ \ code segment.
+
+ op: cs: 0f c, 01 c, 16 c, fc20 w, \ lgdte cs:[fc20] Setup GDT
+
+ op: cr0 bx mov \ Get existing CR0 value
+
+ op: h# 7ffaffd1 # bx and \ PG,AM,WP,NE,TS,EM,MP = 0
+ op: h# 60000001 # bx or \ CD, NW, PE = 1
+\ 1 # bl or \ Set "protected mode" bit
+
+ bx cr0 mov \ Enter protected mode
+ eb c, 0 c, \ jmp to next location to flush prefetch queue
+ \ note: CPL is now 0
+
+ h# 03 port80
+
+
+ \ We are in protected mode, but we are still executing from old
+ \ 16-bit code segment, and will continue to do so until the far jump
+ \ below
+
+[ifdef] debug-reset
+ascii o report
+[then]
+
+ \ set segment registers
+ bx bx xor \ Clear high byte
+ 18 # bl mov \ Data segment selector
+ bx ds mov \ Set segment register
+ bx es mov \ Set segment register
+ bx fs mov \ Set segment register
+ bx gs mov \ Set segment register
+
+[ifdef] debug-reset
+ascii r report
+[then]
+
+ bx ss mov \ Set segment register
+
+[ifdef] debug-reset
+ascii t report
+ascii h report
+[then]
+
+ h# 0f port80
+
+ResetBase .x cr
+ op: ad: ResetBase h# 10 #) far jmp \ Jump to Forth startup
+
+ \ Pad the startup code so that the main entry point ends up at the
+ \ correct address.
+
+ here over - ( adr , size-of-preceding-code )
+
+ \ ffff.fc28 is the location of the code that follows the GDT
+ ffff.fff0 ffff.fc28 - swap - ( address #bytes-to-pad )
+
+ \ The code mustn't extend past ffff.ffc0, because that is where PC
+ \ manufacturers put the 0x10-byte BIOS version string.
+ dup h# 30 - also forth 0< previous abort" Real mode startup code is too big"
+
+ also forth here over h# ff fill previous \ fill with FFs
+ ( #bytes-to-pad ) allot \ Pad out to ffff.fff0
+
+ \ ------->>>>> Main Entry Point
+ \
+ \ ffff.fff0 - This is the hardwired address where the processor jumps
+ \ when it comes out of reset
+
+ 16-bit
+ cli cld \ Turn off interrupts (does not affect NMI)
+ #) jmp \ Relative jump back to ffff.fc28
+ 0 w, 0 c, \ align "pad" to end of ROM
+ loader-version# l, \ version#
+ loader-format# w, \ "format" (>1 when crc present)
+ ffff w, \ placeholder for crc
+
+end-code
+
+end-assembling
+
+writing rmstart.img
+rm-startup here over - ofd @ fputs
+ofd @ fclose
+
+here rm-startup - constant /rm-startup
+/rm-startup h# 400 <> abort" Real mode startup code is not the right size"
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/x86/pc/olpc/via/romreset.bth
===================================================================
--- cpu/x86/pc/olpc/via/romreset.bth (rev 0)
+++ cpu/x86/pc/olpc/via/romreset.bth 2009-04-23 08:06:39 UTC (rev 1154)
@@ -0,0 +1,811 @@
+\ See license at end of file
+purpose: Build file for dropin dispatcher - version for direct ROM startup
+
+command: &builder &this
+build-now
+
+create debug-startup
+
+fload ${BP}/cpu/x86/pc/olpc/via/config.fth \ Address configuration
+
+
+\needs start-assembling fload ${BP}/cpu/x86/asmtools.fth
+\needs write-dropin fload ${BP}/forth/lib/mkdropin.fth
+
+fload ${BP}/cpu/x86/mmuparam.fth
+
+\ startmacros.fth defines some assembler macros that make MSR and I/O port
+\ access very easy by hiding the details of register use.
+
+fload ${BP}/cpu/x86/startmacros.fth
+fload ${BP}/cpu/x86/pc/port80.fth
+
+\ DEBUG
+[ifdef] config-to-port80
+also 386-assembler definitions
+: config-wb
+ h# 77 port80 dup wbsplit port80 port80 over port80
+ config-wb
+;
+previous definitions
+[then]
+
+hex
+
+fload ${BP}/cpu/x86/pc/finddi.fth \ find-dropin and other tools
+
+\ Locations of cacheable areas for cache-as-ram setup
+\ We have to be careful that the instruction-cached area doesn't
+\ collide with the data cache. The instructions, accessed from
+\ ROM, are recoverable, but the data has no backing store so we
+\ mustn't let it be evicted.
+
+\ With the layout below, we should be okay. The L2 cache is big
+\ enough to hold I and D ranges. The dcached range is just below
+\ dropin base and the stack is at the top of that range. The
+\ instructions that we will execute, and their in-line data tables,
+\ are just above dropin base, so they shouldn't collide with the
+\ stack that is near the top of a 64K range.
+
+h# 8000 constant /dcached \ Size of VIA DCache
+h# 8000 constant /icached \ Size of VIA ICache
+dropin-base /dcached - constant dcached-base
+
+h# 10.0000 constant ramtest-start
+h# 20.0000 constant ramtest-end
+create uart-debug-startup
+
+: devfunc ( dev func -- )
+ h# 100 * swap h# 800 * or h# 8000.0000 or
+ [ also assembler ]
+ # ebp mov " masked-config-writes" evaluate #) call
+ [ previous ]
+;
+: end-table 0 c, ;
+
+: mreg ( reg# and or -- ) rot c, swap c, c, ;
+: wait-us ( us -- )
+ " # ax mov usdelay #) call" evaluate
+;
+
+: showreg ( reg# -- )
+ " h# ff port80 d# 200000 wait-us" eval
+ " config-rb al 80 # out d# 1000000 wait-us" eval
+;
+
+start-assembling
+
+label my-entry
+ e9 c, 0 , \ To be patched later
+end-code
+
+[ifdef] uart-debug-startup
+fload ${BP}/cpu/x86/pc/dot.fth \ Numeric output
+[then]
+
+fload ${BP}/cpu/x86/pc/romfind.fth \ find-dropin
+
+hex
+
+\ %ebp contains the config address
+\ %ebp used for merging config write data
+
+label masked-config-writes \ return address points to the table
+ esi pop
+ cld
+ begin
+ al lods \ al: register offset
+ al al or 0<> while
+ al bl mov \ bl: register offset
+
+[ifdef] config-to-port80
+ h# 77 # al mov al h# 80 # out
+ ebp eax mov ah al mov al h# 80 # out
+ bl al mov al h# 80 # out
+[then]
+
+ ebp eax mov \ Config address base
+ bl al mov \ Merge in register number
+ h# ffff.fffc # ax and \ Remove low bits
+ h# cf8 # dx mov \ Config address register port #
+ ax dx out \ Write to config address register
+
+ 4 # dl add \ DX: cfc
+ 3 # bl and \ Byte offset
+ bl dl add \ Config data register port #
+
+ al lods al not \ Get AND mask
+ al al or 0<> if \ Do we need to read-modify-write?
+ al ah mov \ Save mask
+ dx al in \ Get existing value
+[ifdef] config-to-port80
+ al h# 80 # out
+[then]
+ ah al and \ Apply AND mask
+ al ah mov
+ al lods \ Get OR mask
+ ah al or \ Now we have the final value
+ else \ AND mask is 0 so we don't have to R-M-W
+ al lods \ Get final value (== OR mask)
+ then
+
+[ifdef] config-to-port80
+ al h# 80 # out
+[then]
+
+ al dx out \ Write final value to config data register
+ repeat
+ esi push
+ ret
+end-code
+
+[ifdef] uart-debug-startup
+label cominit
+ \ Turn on frame buffer
+ 0 3 devfunc
+ a1 ff 80 mreg \ Not sure why this is needed, the PM says it's the default
+ a7 ff 08 mreg \ Internal GFX allocation
+ end-table
+
+ \ Turn on I/O and memory space access for display controller
+ 1 0 devfunc
+ 04 ff 07 mreg
+ end-table
+
+ 01 3c3 port-wb \ Graphics Chip IO port access on
+ 10 3c4 port-wb 01 3c5 port-wb \ Graphics Chip register protection off
+ 78 3c4 port-wb 86 3c5 port-wb \ South module pad share enable on (80)
+
+ d# 17 0 devfunc
+ \ The following is for UART on VCP port
+ 46 3f 40 mreg
+ \ The following is for UART on DVP port
+ \ 46 3f c0 mreg
+
+ \ Standard COM2 and COM1 IRQ routing
+ b2 00 34 mreg
+
+ \ For COM1 - 3f8 (ff below is 3f8 3 >> 80 or )
+
+ b0 cf 10 mreg
+ b4 00 ff mreg \ 3f8 3 >> 80 or - com base port
+
+ \ For COM2 - 2f8 (df below is 2f8 3 >> 80 or )
+ \ b0 cf 20 mreg
+ \ b5 00 df mreg
+ end-table
+
+ \ The usual setup dance for a PC UART...
+ 01 3fc port-wb \ DTR on
+ 80 3fb port-wb \ Switch to bank 1 to program baud rate
+ 01 3f8 port-wb \ Baud rate divisor low - 115200 baud
+ 00 3f9 port-wb \ Baud rate divisor high - 115200 baud
+ 03 3fb port-wb \ 8 bits, no parity, switch to bank 0
+ 00 3f9 port-wb \ Interrupts off
+ 00 3fa port-wb
+
+ ret
+end-code
+[then]
+
+\ Delay N microseconds, N in ax
+label usdelay
+ cx push
+
+ ax cx mov
+ begin h# 80 # al in loopa
+
+ cx pop
+ ret
+end-code
+
+\ This is the dance you have to do for each DDR rank to turn on the RAM chips
+label DDRinit
+ 11 36b config-wb \ SDRAM NOP
+ 0 #) ax mov \ Access RAM
+ d# 200 wait-us
+
+ 12 36b config-wb \ SDRAM Precharge All
+ 0 #) ax mov \ Access RAM
+
+ 13 36b config-wb \ SDRAM MRS Enable
+ 20200 #) ax mov \ Access RAM for DLL enable - 150 ohm (20020 for 75 ohm)
+ 800 #) ax mov \ Access RAM for DLL reset
+
+ 12 36b config-wb \ SDRAM Precharge All
+ 0 #) ax mov \ Access RAM
+
+ 14 36b config-wb \ SDRAM CBR Cycle Enable
+
+ 8 # cx mov
+ begin
+ 0 #) ax mov
+ d# 100 wait-us
+ loopa
+
+ 13 36b config-wb \ SDRAM MRS Enable
+ 101258 #) ax mov \ Depends on Twr, CL, and Burst Length
+
+ 21e00 #) ax mov \ For 150 ohm; 75 ohm is 21c20
+ 20200 #) ax mov \ For 150 ohm; 75 ohm is 21c20
+
+ 10 36b config-wb \ SDRAM Normal
+
+ ret
+end-code
+
+
+label startup
+\ h# 10 port80
+ 2 92 port-wb \ Enable A20
+ \ External A20GATE is disabled automatically because the internal KBC is on by default (cfg reg 8851 bit 0)
+
+\ Enable cache as RAM
+ cr0 ax mov h# 4000.0000 bitset ax cr0 mov invd \ Disable cache
+
+ 00000000.00000c00. 2ff set-msr \ Enable fixed and variable MTRRs in DefType
+ 00000000.00000000. 250 set-msr \ Clear fixed MTRR
+ 258 wmsr 259 wmsr 268 wmsr 269 wmsr 26a wmsr \ Fixed MTRRs
+ 26b wmsr 26c wmsr 26d wmsr 26e wmsr 26f wmsr \ Fixed MTRRs
+ 200 wmsr 201 wmsr 202 wmsr 203 wmsr 204 wmsr \ Variable MTRRs
+ 205 wmsr 206 wmsr 207 wmsr 208 wmsr 209 wmsr \ Variable MTRRs
+ 20a wmsr 20b wmsr 20c wmsr 20d wmsr 20e wmsr \ Variable MTRRs
+ 20f wmsr \ Last variable one
+
+ dcached-base 6 + 0 200 set-msr \ Dcache base address, write back
+ /dcached negate h# 800 + f 201 set-msr \ Dcache size
+ dropin-base 6 + 0 202 set-msr \ ROM base address
+ /icached negate h# 800 + f 203 set-msr \ Icache size
+
+ 00000000.00000800. 2ff set-msr \ Enable variable MTRRs in DefType
+
+
+ cr0 ax mov h# 6000.0000 bitclr ax cr0 mov invd \ Cache on
+
+ cld
+
+ \ Access ROM to load it into the dcache
+ dropin-base # esi mov
+ /icached 4 / # ecx mov
+ rep eax lods
+
+ \ Access "RAM" area to load it into the dcache
+ dcached-base # esi mov
+ /dcached 4 / # ecx mov
+ rep eax lods
+
+ \ Put the stack pointer at the top of the dcached area
+ dcached-base /dcached + 4 - # esp mov
+ ds ax mov ax ss mov
+
+\ We are now running from cache, and can use the stack
+
+\ h# 20 port80 d# 300000 wait-us
+
+\ cache_as_ram_auto.c: amd64_main()
+
+ 01 004f config-wb \ Enable device 0 multiple functions
+
+\ 8898 config-rb al 80 # out d# 300000 wait-us
+
+ 00 8898 config-wb \ Disable BIOS init timer GP3
+
+[ifdef] uart-debug-startup
+ cominit #) call
+ carret report
+ linefeed report
+[then]
+
+\ This is a device ID backdoor to fake out the ID so Ubuntu will install
+\ 8879 config-rb h# 40 # al or al dx out \ I don't know what this is, but coreboot does it
+
+1 [if]
+ \ This turns an OS reboot into a real cold start - from coreboot
+ 4001 8888 config-ww \ Set ACPI base address
+ 84 8881 config-wb \ Enable ACPI regs and guard RTC against power glitches
+ 4004 port-rw \ Get APCI Status register
+ d# 10 # ax shr 7 # ax and 1 # ax cmp <> if \ Not a wakeup from S3
+ 380 config-rb ax ax or 0<> if \ C-page shadowing not on yet
+ 6 cf9 port-wb \ Force a full system reset
+ then
+ then
+[then]
+
+ \ enable_mainboard_devices()
+\ 41 8f4f config-wb \ Enable P2P Bridge Header for External PCI Bus (coreboot value)
+ 43 8f4f config-wb \ As above, plus support extended PCIe config space
+
+\ 4f6 config-rb \ Get Northbridge revision ... don't need it because the
+ \ init table contains no revision-specific entries
+
+ \ via_pci_inittable(NBrevision,mNbStage1InitTbl)
+
+ \ Enable extended config space for PCIe
+ 0 5 devfunc \ NB_APIC
+ 61 ff 0e mreg \ Set Exxxxxxx as PCIe MMIO config range
+ 60 f4 0b mreg \ Support extended cfg address of PCIe (preserve 28 bits)
+ end-table
+
+ 0 2 devfunc \ HOST CPU CTL
+ 50 1f 08 mreg \ Request phase ctrl: Dynamic Defer Snoop Stall Count = 8
+ 51 ff 7c mreg \ CPU I/F Ctrl-1: Disable Fast DRDY and RAW
+ 52 cb cb mreg \ CPU I/F Ctrl-2: Enable all for performance
+ 53 ff 44 mreg \ Arbitration: Host/Master Occupancy timer = 4*4 HCLK
+ 54 1e 1c mreg \ Misc Ctrl: Enable 8QW burst Mem Access
+
+ 55 06 04 mreg \ Miscellaneous Control 2
+ 56 f7 63 mreg \ Write Policy 1
+ 5d ff a2 mreg \ Write Policy
+ 5e ff 88 mreg \ Bandwidth Timer
+ 5f 46 46 mreg \ CPU Misc Ctrl
+
+ 96 0b 0a mreg \ Write Policy
+ 98 c1 41 mreg \ Bandwidth Timer
+ 99 0e 06 mreg \ CPU Misc Ctrl
+ 97 ff 00 mreg \ APIC Related Control
+ end-table
+
+ 0 3 devfunc
+ 86 d6 29 mreg \ SMM and APIC Decoding: enable APIC, MSI and SMRAM A-Seg
+ end-table
+
+\ Detection.c
+\ DRAMCmdRate
+
+ 0 3 devfunc
+ 50 11 00 mreg \ Use stable 2T command rate
+ end-table
+
+\ h# 23 port80 d# 300000 wait-us
+
+\ FreqSetting.c : DRAMFreqSetting()
+ \ The following register is undocumented. coreboot has this comment:
+ \ Must use "CPU delay" to make sure VLINK is dis-connect
+ 0 7 devfunc 47 00 04 mreg end-table d# 20 wait-us
+ 0 3 devfunc 90 07 07 mreg end-table d# 20 wait-us \ First set DRAM Freq to invalid
+ 0 3 devfunc 90 07 04 mreg end-table d# 20 wait-us \ 266 MHz
+ 0 3 devfunc 6b d0 c0 mreg end-table d# 20 wait-us \ PLL Off
+ 0 3 devfunc 6b 00 10 mreg end-table d# 20 wait-us \ PLL On
+ 0 3 devfunc 6b c0 00 mreg end-table \ Adjustments off
+ 0 7 devfunc 47 04 00 mreg end-table \ disable V_LINK Auto-Disconnect
+
+\ h# 24 port80 d# 300000 wait-us
+
+\ TimingSetting.c
+ 0 3 devfunc
+ 61 ff 55 mreg \ Trfc, Trrd
+ 62 ff 8a mreg \ CL, Trp, Tras
+ 63 ff 49 mreg \ Twr, Twtr, Trtp
+ 64 ff 66 mreg \ Trp, Trcd
+ end-table
+
+\ DRDR_BL.c
+\ DRAMDRDYsetting
+ 0 2 devfunc
+ 60 ff aa mreg \ DRDY Timing Control 1 for Read Line
+ 61 ff 0a mreg \ DRDY Timing Control 2 for Read Line
+ 62 ff 00 mreg \ Reserved, probably channel B
+ 63 ff aa mreg \ DRDY Timing Control 1 for Read QW
+ 64 ff 0a mreg \ DRDY Timing Control 2 for Read QW
+ 65 ff 00 mreg \ Reserved, probably channel B
+ 66 ff 00 mreg \ Burst DRDR Timing Control for Second cycle in burst
+ 67 ff 00 mreg \ Reserved, probably channel B
+ 54 0a 08 mreg \ Misc ctl 1 - special mode for DRAM cycles
+ 51 00 80 mreg \ Last step - enable DRDY timing - should the mask be f7 ?
+ end-table
+
+\ DRAMBurstLength
+ 0 3 devfunc
+ 6c 08 08 mreg \ Burst length 8
+\ DrivingSetting.c
+\ DrivingODT
+ d0 ff 88 mreg \ Pull up/down Termination strength
+ d6 fc fc mreg \ DCLK/SCMD/CS drive strength
+ d3 fb 01 mreg \ Compensation control - enable DDR Compensation
+ 9e 30 10 mreg \ SRAM ODT Control 1 - 1T wait state turnaround
+ 9f 11 11 mreg \ SDRAM ODT Control 2 - Late extension values
+ d5 a0 00 mreg \ DQ/DQS Burst and ODT Range Select - disable bursts for channel A
+ d7 80 00 mreg \ SCMD/MA Burst - Disable SDMD/MAA burst
+ d5 0c 04 mreg \ Enable DRAM MD Pad ODT of Channel A High 32 bits
+
+ 9c ff e1 mreg \ ODT Lookup table
+ d4 36 30 mreg \ ChannelA MD ODT dynamic-on
+ 9e 00 01 mreg \ Enable Channel A differential DQS Input
+ 9e 00 80 mreg \ Enable ODT controls
+
+\ DrivingDQS,DQ,CS,MA,DCLK
+ e0 ff ee mreg \ DQS A
+ e1 ff 00 mreg \ DQS B
+ e2 ff ac mreg \ DQ A
+ e3 ff 00 mreg \ DQ B
+ e4 ff 44 mreg \ CS A
+ e5 ff 00 mreg \ CS B
+ e6 ff ff mreg \ MCLK A
+ e7 ff 88 mreg \ MCKL B
+ e8 ff 86 mreg \ MA A
+ e9 ff 00 mreg \ MA B
+
+\ ClkCtrl.c (register tables in mainboard/via/6413e/DrivingClkPhaseData.c)
+\ DutyCycleCtrl
+ ec ff 30 mreg \ DQS/DQ Output duty control
+ ee f0 00 mreg \ DCLK Output duty control
+ ef 30 00 mreg \ DQ CKG Input Delay - going with Phoenix value; coreboot uses 30
+
+\ DRAMClkCtrl
+\ WrtDataPhsCtrl
+ 74 07 00 mreg \ DQS Phase Offset
+ 75 07 00 mreg \ DQ Phase Offset
+ 76 ef 07 mreg \ Write data Phase control
+ 8c 03 03 mreg \ DQS Output Control
+
+\ ClkPhsCtrlFBMDDR2
+ 91 07 00 mreg \ DCLK Phase
+ 92 07 03 mreg \ CS/CKE Phase
+ 93 07 04 mreg \ SCMD/MA Phase
+
+\ DQDQSOutputDlyCtrl
+ f0 ff 00 mreg \ Group A0/1
+ f1 ff 00 mreg \ Group A2/3
+ f2 ff 00 mreg \ Group A4/5
+ f3 ff 00 mreg \ Group A6/7
+
+\ DQSInputCaptureCtrl
+ 77 bf 8a mreg \ DQS Input Delay - Manual
+ 78 3f 03 mreg \ DQS Input Capture Range Control A
+ 7a 0f 00 mreg \ Reserved
+ 7b 7f 20 mreg \ Read Data Phase Control
+
+\ DCLKPhsCtrl
+ 99 1e 12 mreg \ MCLKOA[4,3,0] outputs
+ end-table
+
+\ DevInit.c
+\ DRAMRegInitValue
+
+ 0 3 devfunc
+ 50 ee ee mreg \ DDR default MA7 for DRAM init
+ 51 ee 60 mreg \ DDR default MA3 for CHB init
+ 52 ff 33 mreg \ DDR use BA0=M17, BA1=M18,
+ 53 ff 3F mreg \ DDR BA2=M19
+
+ 54 ff 00 mreg \ default PR0=VR0; PR1=VR1
+ 55 ff 00 mreg \ default PR2=VR2; PR3=VR3
+ 56 ff 00 mreg \ default PR4=VR4; PR5=VR5
+ 57 ff 00 mreg \ default PR4=VR4; PR5=VR5
+
+ 60 ff 00 mreg \ disable fast turn-around
+ 65 ff D9 mreg \ AGP timer = D; Host timer = 8;
+ 66 ff 88 mreg \ DRAMC Queue Size = 4; park at the last bus owner,Priority promotion timer = 8
+ 68 ff 0C mreg
+ 69 0F 04 mreg \ set RX69[3:0]=0000b
+ 6A ff 00 mreg \ refresh counter
+ 6E 07 80 mreg \ must set 6E[7],or else DDR2 probe test will fail
+ 85 ff 00 mreg
+ 40 ff 00 mreg
+ end-table
+
+ 80 4a3 config-wb \ Enable toggle reduction on MA/SCMD per coreboot
+
+\ DRAMInitializeProc
+
+ 0 3 devfunc
+ 6c 00 04 mreg \ Enable channel A only
+
+ 54 ff 80 mreg \ Enable rank 0, disable rank 1
+ 55 ff 00 mreg \ Disable ranks 2 and 3
+ 40 ff 10 mreg \ Rank 0 top
+ 48 ff 00 mreg \ Rank 0 base
+ end-table
+
+\ h# 25 port80 d# 300000 wait-us
+
+ DDRinit #) call
+
+ h# 11 port80
+
+ 0 3 devfunc
+ 40 ff 00 mreg \ Rank 1 top back to 0 to work on other ranks
+
+ 54 ff 09 mreg \ Enable rank 1
+ 55 ff 00 mreg \ Disable ranks 2 and 3
+ 41 ff 10 mreg \ Rank 1 top
+ 49 ff 00 mreg \ Rank 1 base
+ end-table
+
+ DDRinit #) call
+
+ 0 3 devfunc
+ 41 ff 00 mreg \ Rank 1 top back to 0 to work on other ranks
+ end-table
+
+ h# 14 port80
+
+0 [if] \ This is for a DIMM in the other socket
+ 0 3 devfunc
+ 54 ff 00 mreg \ Disable ranks 0,1
+ 55 ff a0 mreg \ Enable Rank 2
+ 42 ff 10 mreg \ Rank 2 top
+ 4a ff 00 mreg \ Rank 2 base
+ end-table
+
+ DDRinit #) call
+
+ 0 3 devfunc
+ 42 ff 00 mreg \ Rank 2 top back to 0 to work on other ranks
+ 54 ff 00 mreg \ Disable ranks 0,1
+ 55 ff 0b mreg \ Enable Rank 3
+ 43 ff 10 mreg \ Rank 3 top
+ 4b ff 00 mreg \ Rank 3 base
+ end-table
+
+ DDRinit #) call
+
+ 0 3 devfunc
+ 43 ff 00 mreg \ Rank 3 top back to 0 to work on other ranks
+ end-table
+[then]
+
+ 0 3 devfunc
+ 69 03 03 mreg \ Reinstate page optimizations (03) - FF #ranks
+
+\ RankMap.c
+\ DRAMBankInterleave
+\ (see 69 above)
+ 87 ff 00 mreg \ Channel B #banks or some such - FF BA
+\ SizingMATypeM
+
+ 50 ff 20 mreg \ MA Map type - ranks 0/1 type 1 - 2 bank bits, 10 column bits
+ 51 ff 60 mreg \ "Reserved"
+ 52 ff 33 mreg \ Bank interleave on A17, A18, and
+ 53 ff 3f mreg \ A19 (but BA2 off because 4 banks), Rank interleave on A20 and A21
+ \ Different interleave bits might improve performance on some workloads
+
+ 54 ff 89 mreg \ Rank map A 0/1
+ 55 ff 00 mreg \ Rank map A 2/3
+ 56 ff 00 mreg \ Rank map B ?
+ 57 ff 00 mreg \ Rank map B ?
+
+ 40 ff 04 mreg \ Rank top 0
+ 41 ff 08 mreg \ Rank top 1
+ 42 ff 00 mreg \ Rank top 2
+ 43 ff 00 mreg \ Rank top 3
+
+ 48 ff 00 mreg \ Rank base 0
+ 49 ff 04 mreg \ Rank base 1
+ 4a ff 00 mreg \ Rank base 2
+ 4b ff 00 mreg \ Rank base 3
+ end-table
+
+ 20 8f60 config-wb \ DRAM Bank 7 ending address - controls DMA upstream
+ 0388 config-rb ax bx mov 0385 config-setup bx ax mov al dx out \ Copy Low Top from RO reg 88 to reg 85
+ 0388 config-rb ax bx mov 8fe5 config-setup bx ax mov al dx out \ Copy Low Top from RO reg 88 to SB Low Top e5
+
+0 [if] \ Very simple memtest
+ax ax xor
+h# 12345678 # bx mov
+bx 0 [ax] mov
+h# 5555aaaa # 4 [ax] mov
+0 [ax] dx mov
+dx bx cmp = if
+ ascii G report ascii 2 report h# 20 report
+else
+ dx ax mov dot #) call
+ ascii B report ascii 2 report h# 20 report
+ hlt
+then
+[then]
+
+ \ Low 2 bits of 86:
+ \ x1 to write to SMM shadow memory behind VGA
+ \ 00 to run - Axxxxx hits VGA in normal mode, hits shadow DRAM in SMM
+ \ 01 to access VGA when in SMM (data cycles only)
+
+\ d# 17 7 devfunc
+\ e6 ff 07 mreg \ Enable Top, High, and Compatible SMM
+\ end-table
+
+
+\ DQSSearch.c
+\ DRAMDQSOutputSearch
+ 0 3 devfunc
+ 70 ff 00 mreg \ Output delay
+ 71 ff 04 mreg
+
+\ DRAMDQSInputSearch
+ 77 ff 00 mreg \ Input delay auto
+
+\ FinalSetting.c
+\ RefreshCounter
+ 6a ff 86 mreg \ Refresh interval - FF frequency
+
+\ DRAMRegFinalValue
+ 60 00 d0 mreg \ Fast turn-around
+ 66 30 80 mreg \ DRAMC queue = 4 (already set to 88 up above), park at last owner
+ 69 00 07 mreg \ Enable multiple page
+ 95 ff 0d mreg \ Self-refresh controls
+ 96 f0 a0 mreg \ Auto self-refresh stuff
+ fb ff 3e mreg \ Dynamic clocks
+ fd ff a9 mreg \ Dynamic clocks
+ fe ff 0f mreg \ Chips select power saving for self-refresh
+ ff ff 3d mreg \ DSQB input delay, SCMD enabled
+ 96 0f 03 mreg \ Enable self-refresh for ranks 0 and 1
+ end-table
+
+ 0 4 devfunc \ PM_table
+ a0 f0 f0 mreg \ Enable dynamic power management
+ a1 e0 e0 mreg \ Dynamic power management for DRAM
+ a2 ff fe mreg \ Dynamic clock stop controls
+ a3 80 80 mreg \ Toggle reduction on
+ a5 81 81 mreg \ "Reserved"
+ end-table
+
+1 [if]
+ax ax xor
+h# 12345678 # bx mov
+bx 0 [ax] mov
+h# 5555aaaa # 4 [ax] mov
+0 [ax] dx mov
+dx bx cmp <> if ascii B report ascii A report ascii D report begin again then
+[then]
+
+\ fload ${BP}/cpu/x86/pc/ramtest.fth
+
+\ UMARamSetting.c
+\ SetUMARam
+ 0 3 devfunc
+ a1 00 80 mreg \ Enable internal GFX
+ a2 ff ee mreg \ Set GFX timers
+ a4 ff 01 mreg \ GFX Data Delay to Sync with Clock
+ a6 ff 76 mreg \ Page register life timer
+ a7 ff 8c mreg \ Internal GFX allocation
+ b3 ff 9a mreg \ Disable read past write
+ de ff 06 mreg \ Enable CHA and CHB merge mode (but description says this value disable merging!)
+ end-table
+
+ 0 3 devfunc
+ a1 70 40 mreg \ Set frame buffer size to 64M (8M:10, 16M:20, 32M:30, etc) - fbsize
+ end-table
+
+ 1 0 devfunc
+ \ Reg 1b2 controls the number of writable bits in the BAR at 810
+ b2 ff 70 mreg \ Offset of frame buffer, depends on size - fbsize
+ 04 ff 07 mreg \ Enable IO and memory access to display
+ end-table
+
+ d000.0000 810 config-wl \ S.L. Base address
+ f000.0000 814 config-wl \ MMIO Base address
+ cd01 3a0 config-ww \ Set frame buffer size and CPU-relative address and enable
+
+ 0 0 devfunc
+ d4 00 03 mreg \ Enable MMIO and S.L. access in Host Control device
+ fe 00 10 mreg \ 16-bit I/O port decoding for VGA (no aliases)
+ end-table
+
+ 1 0 devfunc
+ b0 07 03 mreg \ VGA memory selection (coreboot uses 03, Phoenix 01. I think 03 is correct)
+ end-table
+
+ 01 3c3 port-wb \ Graphics chip IO port access on
+ 10 3c4 port-wb 01 3c5 port-wb \ Turn off register protection
+ 67 3c2 port-wb \ Enable CPU Display Memory access (2), use color not mono port (1)
+
+ 68 3c4 port-wb e0 3c5 port-wb \ Size of System Local Frame Buffer - Value depends on frame buffer size - fbsize
+ \ 00:512MB 80:256MB c0:128MB e0:64MB f0:32MB f8:16MB fc:8MB fe:4MB ff:2MB
+
+ \ These 2 are scratch registers that communicate with the VGA BIOS
+ 3d 3d4 port-wb 74 3d5 port-wb \ Value depends on DIMM frequency - used by VGA BIOS
+ 39 3c4 port-wb 10 3c5 port-wb \ BIOS Reserved Register 0 - FBsize_MiB/4 - fbsize - VGA BIOS
+
+ 5a 3c4 port-wb 01 3c5 port-wb \ Point to secondary registers
+ 4c 3c4 port-wb 83 3c5 port-wb \ LCDCK Clock Synthesizer Value 2
+ 5a 3c4 port-wb 00 3c5 port-wb \ Point back to primary registers
+
+ 6d 3c4 port-wb e0 3c5 port-wb \ Base address [28:21] of SL in System Memory - base is 1c00.0000 - fbsize, memsize
+ 6e 3c4 port-wb 00 3c5 port-wb \ Base address [36:29] of SL in System Memory
+ 6f 3c4 port-wb 00 3c5 port-wb \ Base address [47:37] of SL in System Memory
+
+ 36 3c4 port-wb 11 3c5 port-wb \ Subsystem Vendor ID 1
+ 35 3c4 port-wb 06 3c5 port-wb \ Subsystem Vendor ID 0
+ 38 3c4 port-wb 51 3c5 port-wb \ Subsystem ID 1
+ 37 3c4 port-wb 22 3c5 port-wb \ Subsystem ID 0
+
+ f3 3c4 port-wb 00 3c5 port-wb \ 1a for snapshot mode
+ f3 3d4 port-wb 12 3c5 port-wb \ Snapshot mode control - 1a for snapshot mode
+
+\ cache_as_ram_auto.c : enable_shadow_ram
+ 0 3 devfunc
+ 80 ff ff mreg \ Enable R/W memory access to Cxxxx bank
+ 81 ff ff mreg \ Enable R/W memory access to Dxxxx bank
+ 82 ff ff mreg \ Enable R/W memory access to Exxxx bank
+ 83 30 30 mreg \ Enable R/W memory access to Fxxxx bank (30), no memory hole (0c), SMM switching of Axxxx bank (03)
+\ 86 ff 85 mreg \ 4 MiB Top SMM Memory (80), enable top SMM memory (04), enable compatible SMM (01)
+ end-table
+
+ h# 1c00.0000 # mem-info-pa 4 + #) mov \ Top of memory
+
+ long-offsets on
+
+ h# 1e port80
+
+\ Fix the MTRRs so the real RAM is cacheable, instead of the fake nonexistent area
+ cr0 ax mov h# 6000.0000 bitset ax cr0 mov \ Cache off
+
+ 0000.0000.0000.0c00. 2ff set-msr \ Enable fixed and variable MTRRs in DefType
+
+ 0000.0000.0000.0006. 200 set-msr \ RAM starting at 0
+ 0000.000f.c000.0800. 201 set-msr \ 1 GiB
+ 0000.0000.ff00.0006. 202 set-msr \ ROM in last meg
+ 0000.000f.ff00.0800. 203 set-msr \ 1 MiB
+ 0000.0000.d000.0001. 204 set-msr \ Frame buffer - Write Combining mode
+ 0000.000f.f000.0800. 205 set-msr \ 256 MB
+
+ 0606.0606.0606.0606. 250 set-msr \ Cache 00000-7FFFF
+ 0606.0606.0606.0606. 258 set-msr \ Cache 80000-9FFFF
+ 0000.0000.0000.0000. 259 set-msr \ Don't Cache VGA range from A0000 to BFFFF
+ 0606.0606.0606.0606. 268 set-msr \ Cache C0000-C7FFF
+ 0606.0606.0606.0606. 269 set-msr \ Cache C8000-CFFFF
+ 0606.0606.0606.0606. 26a set-msr \ Cache D0000-D7FFF
+ 0606.0606.0606.0606. 26b set-msr \ Cache D8000-DFFFF
+ 0606.0606.0606.0606. 26c set-msr \ Cache E0000-E7FFF
+ 0606.0606.0606.0606. 26d set-msr \ Cache E8000-EFFFF
+ 0606.0606.0606.0606. 26e set-msr \ Cache F0000-F7FFF
+ 0606.0606.0606.0606. 26f set-msr \ Cache F8000-FFFFF
+
+ cr0 ax mov h# 6000.0000 bitclr ax cr0 mov \ Cache on
+ h# 10.0000 # sp mov \ Move stack to real memory
+
+\ Cache is now back on, with the final MTRR setup
+
+ \ Now we can use the stack and do conventional subroutine calls
+
+\ Enable the keyboard controller
+
+\ 8851 config-rb 2 # ax or ax bx mov
+\ 8851 config-setup bx ax mov al dx out \ Enable the keyboard configuration port
+\ e2 2e port-wb 7 2f port-wb
+
+\ XXX need to set some registers in D17F7 "SNMIC" per chapter 21 of the BIOS Porting Guide
+
+ h# 1f port80
+[ifdef] uart-debug-startup
+ char F report
+ char o report
+ char r report
+[then]
+
+ fload ${BP}/cpu/x86/pc/resetend.fth
+end-code
+
+also 386-assembler
+startup my-entry put-branch
+previous
+
+end-assembling
+
+writing romreset.di
+asm-base here over - 0 " reset" write-dropin
+ofd @ fclose
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2009 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/x86/pc/olpc/via/smbus.fth
===================================================================
--- cpu/x86/pc/olpc/via/smbus.fth (rev 0)
+++ cpu/x86/pc/olpc/via/smbus.fth 2009-04-23 08:06:39 UTC (rev 1154)
@@ -0,0 +1,58 @@
+h# xxx constant smbus-io-base
+: smb-reg@ ( reg# -- value ) smbus-io-base + c@ ;
+: smb-reg! ( value reg# -- ) smbus-io-base + c! ;
+
+: smb-hostdata0@ ( -- byte ) 5 smb-reg@ ;
+: smb-hostdata0! ( byte -- ) 5 smb-reg! ;
+: smb-hostctl! ( byte -- ) 2 smb-reg! ;
+: smb-hostcmd! ( byte -- ) 3 smb-reg! ;
+: smb-xmitadr! ( byte -- ) 4 smb-reg! ;
+: smbus-delay ( -- ) 1 us ;
+: smbus-wait ( -- )
+ d# 1,000,000 0 do
+ smbus-delay
+ 0 smb-reg@ 1 and 0= if unloop exit then
+ loop
+ ." SMBUS timeout" cr
+;
+: smbus-reset ( -- )
+ h# ff 0 smb-reg!
+ 0 smb-hostdata0! \ Clear host data port
+ smbus-wait
+;
+: smb-fill ( adr len -- )
+;
+
+: ics-value0 ( -- adr len dev )
+ " "(0d 00 3f cd 7f bf 1a 2a 01 0f 0b 80 8d 9b)" h# d2
+;
+: ics-value1 ( -- adr len dev )
+ " "(08 ff 3f 00 00 ff ff ff ff)" h# d4
+;
+: smbus-write ( adr len dev -- )
+ smbus-reset
+ 0 smb-reg@ drop \ Read to reset block transfer counter
+ dup smb-xmitadr! ( adr len ) \ Set transmit address
+ tuck bounds ?do i c@ 7 smb-reg! loop ( len )
+ 0 smb-hostcmd! ( len ) \ Host command
+ smb-hostdata0! ( ) \ Length
+ h# 74 smb-hostctl! ( )
+ smbus-wait ( )
+ smbus-reset ( )
+;
+: get-spd-data ( offset dimm -- byte )
+ smbus-reset
+ 7 and 2* h# a1 or ( offset dev )
+ smb-xmitadr! ( offset )
+ smb-hstcmd! ( )
+ h# 48 smb-hstctl! ( )
+ smbus-wait
+ smb-hostdata0@ ( byte )
+;
+: enable-smbus ( -- )
+ h# 8894 config-b@ h# 80 invert and h# 8894 config-b! \ Clock from 14 MHz divider
+ smbus-io-base 1 or h# 88d0 config-w!
+ 5 h# 88d2 config-b! \ Clock source (bit meaning is unclear), enable SMBUS HC
+ 3 h# 8804 config-w! \ Enable in PCI command register
+ smbus-reset
+;
Added: cpu/x86/pc/olpc/via/sourceurl.fth
===================================================================
--- cpu/x86/pc/olpc/via/sourceurl.fth (rev 0)
+++ cpu/x86/pc/olpc/via/sourceurl.fth 2009-04-23 08:06:39 UTC (rev 1154)
@@ -0,0 +1,8 @@
+\ Make a file containing the URL of the source code
+
+show-rebuilds? false to show-rebuilds? \ We don't need to see these commands
+
+" svn info ../../../../../.. | grep URL: | cut -d ' ' -f 2 | tr \\n ' ' >sourceurl" $sh
+" svnversion -n ../../../../../.. >>sourceurl" $sh
+
+to show-rebuilds?
Added: cpu/x86/pc/olpc/via/southbridge.fth
===================================================================
--- cpu/x86/pc/olpc/via/southbridge.fth (rev 0)
+++ cpu/x86/pc/olpc/via/southbridge.fth 2009-04-23 08:06:39 UTC (rev 1154)
@@ -0,0 +1,51 @@
+hex
+: sb-setup ( -- )
+44 8840 config-b!
+f0 8842 config-b!
+0b 8843 config-b!
+01 884d config-b!
+18 884e config-b!
+c0 8850 config-b!
+4d 8851 config-b!
+19 8852 config-b!
+80 8853 config-b!
+a0 8855 config-b!
+b9 8856 config-b!
+a0 8857 config-b!
+60 8858 config-b!
+53 885b config-b!
+80 8868 config-b!
+d0 886a config-b!
+fe 886b config-b!
+d8 886e config-b!
+06 8870 config-b!
+11 8871 config-b!
+37 8872 config-b!
+33 8873 config-b!
+20 8880 config-b!
+da 8884 config-b!
+40 8885 config-b!
+1f 888a config-b!
+18 888d config-b!
+08 889a config-b!
+88 889b config-b!
+30 88b0 config-b!
+7f 88b4 config-b!
+5d 88b5 config-b!
+40 88b7 config-b!
+80 88b8 config-b!
+40 88b9 config-b!
+44 88ba config-b!
+77 88bb config-b!
+d3 88bd config-b!
+fe 88be config-b!
+90 88bf config-b!
+41 88d1 config-b!
+01 88d2 config-b!
+eb 88e2 config-b!
+a0 88e4 config-b!
+60 88e5 config-b!
+20 88e6 config-b!
+80 88e7 config-b!
+04 88fc config-b!
+;
Added: cpu/x86/pc/olpc/via/usb.fth
===================================================================
--- cpu/x86/pc/olpc/via/usb.fth (rev 0)
+++ cpu/x86/pc/olpc/via/usb.fth 2009-04-23 08:06:39 UTC (rev 1154)
@@ -0,0 +1,118 @@
+purpose: USB elaborations for the BIOS loaded OFW
+\ See license at end of file
+
+0 config-int usb-delay \ Milliseconds to wait before set-address
+
+devalias u /usb/disk
+
+\ Like $show-devs, but ignores pagination keystrokes
+: $nopage-show-devs ( nodename$ -- )
+ ['] exit? behavior >r ['] false to exit?
+ $show-devs
+ r> to exit?
+;
+
+: (probe-usb2) ( -- )
+ " device_type" get-property if exit then
+[ifdef] use-usb-debug-port
+ \ I haven't figured out how to turn on the EHCI cleanly
+ \ when the Debug Port is running
+ dbgp-off
+[then]
+ get-encoded-string " ehci" $= if
+ pwd$ open-dev ?dup if close-dev then
+ then
+;
+: (show-usb2) ( -- )
+ " device_type" get-property if exit then
+ get-encoded-string " ehci" $= if
+ pwd$ $nopage-show-devs
+ then
+;
+: (probe-usb1) ( -- )
+ " device_type" get-property if exit then
+ get-encoded-string 2dup " uhci" $= >r " ohci" $= r> or if
+ pwd$ open-dev ?dup if close-dev then
+ then
+;
+: (show-usb1) ( -- )
+ " device_type" get-property if exit then
+ get-encoded-string 2dup " uhci" $= >r " ohci" $= r> or if
+ pwd$ $nopage-show-devs
+ then
+;
+: probe-usb ( -- )
+ ." USB2 devices:" cr
+ " /" ['] (probe-usb2) scan-subtree
+ " /" ['] (show-usb2) scan-subtree
+
+ ." USB1 devices:" cr
+ " /" ['] (probe-usb1) scan-subtree
+ " /" ['] (show-usb1) scan-subtree
+;
+alias p2 probe-usb
+
+: ?usb-keyboard ( -- )
+ " keyboard" expand-alias if ( devspec$ )
+ drop " /usb" comp 0= if ( )
+ red-letters ." Using USB keyboard." cr black-letters
+ " keyboard" input
+ exit
+ then
+ then
+ " /usb/serial" open-dev ?dup if
+ red-letters ." Using USB serial console." cr black-letters
+ dup set-stdin set-stdout
+ then
+;
+
+\ Unlink every node whose phys.hi component matches port
+: port-match? ( port -- flag )
+ get-unit if drop false exit then
+ get-encoded-int =
+;
+: rm-usb-children ( port -- )
+ device-context? 0= if drop exit then
+ also ( port )
+ 'child ( port prev )
+ first-child begin while ( port prev )
+ over port-match? if ( port prev )
+ 'peer link@ over link! ( port prev ) \ Disconnect
+ else ( port prev )
+ drop 'peer ( port prev' )
+ then ( port prev )
+ next-child repeat ( port prev )
+ 2drop ( )
+ previous definitions
+;
+
+: usb-quiet ( -- )
+ [ ' go-hook behavior compile, ] \ Chain to old behavior
+ " usb1" " reset-usb" execute-device-method drop
+ " usb2" " reset-usb" execute-device-method drop
+;
+' usb-quiet to go-hook
+
+\ LICENSE_BEGIN
+\ Copyright (c) 2007 FirmWorks
+\
+\ Permission is hereby granted, free of charge, to any person obtaining
+\ a copy of this software and associated documentation files (the
+\ "Software"), to deal in the Software without restriction, including
+\ without limitation the rights to use, copy, modify, merge, publish,
+\ distribute, sublicense, and/or sell copies of the Software, and to
+\ permit persons to whom the Software is furnished to do so, subject to
+\ the following conditions:
+\
+\ The above copyright notice and this permission notice shall be
+\ included in all copies or substantial portions of the Software.
+\
+\ THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+\ EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+\ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+\ NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
+\ LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
+\ OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
+\ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+\
+\ LICENSE_END
Added: cpu/x86/pc/olpc/via/versions.fth
===================================================================
--- cpu/x86/pc/olpc/via/versions.fth (rev 0)
+++ cpu/x86/pc/olpc/via/versions.fth 2009-04-23 08:06:39 UTC (rev 1154)
@@ -0,0 +1,31 @@
+\ Version numbers of items included in the OLPC firmware image
+
+\ The overall firmware revision
+macro: FW_MAJOR A
+macro: FW_MINOR 00
+
+\ The EC microcode
+macro: EC_VERSION e34
+
+\ Alternate command for getting EC microcode, for testing new versions.
+\ Temporarily uncomment the line and modify the path as necessary
+\ macro: GET_EC cp pq2e18c.img ec.img
+
+macro: KEYS mpkeys
+\ macro: KEYS testkeys
+
+\ The wireless LAN module firmware
+macro: WLAN_RPM ${WLAN_VERSION}.olpc1
+macro: WLAN_VERSION 5.110.22.p23
+
+\ The bios_verify image
+macro: CRYPTO_VERSION 0.2
+
+\ The multicast NAND updater code version
+\ Use a specific git commit ID for a formal release or "test" for development.
+\ With a specific ID, mcastnand.bth will download a tarball without .git stuff.
+\ With "test", mcastnand.bth will clone the git head if build/multicast-nand/
+\ is not already present, then you can modify the git subtree as needed.
+macro: MCNAND_VERSION 0c73b4a084a27f0687b152dd0395c67fdf54b10f
+\ macro: MCNAND_VERSION test
+\ macro: MCNAND_VERSION HEAD
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