[openfirmware] [commit] r1896 - in cpu/arm: . mmp2 mmp2/build

repository service svn at openfirmware.info
Thu Jul 22 09:02:07 CEST 2010


Author: wmb
Date: Thu Jul 22 09:02:07 2010
New Revision: 1896
URL: http://tracker.coreboot.org/trac/openfirmware/changeset/1896

Log:
ARM MMP2 - can now boot Linux.

Added:
   cpu/arm/mmp2/build/Linux-debug.txt
Modified:
   cpu/arm/boot.fth
   cpu/arm/mmp2/addrs.fth
   cpu/arm/mmp2/boot.fth
   cpu/arm/mmp2/build/Makefile
   cpu/arm/mmp2/devices.fth
   cpu/arm/mmp2/fw.bth
   cpu/arm/mmp2/mmuon.fth
   cpu/arm/scc.fth
   cpu/arm/target.fth

Modified: cpu/arm/boot.fth
==============================================================================
--- cpu/arm/boot.fth	Thu Jul 22 08:54:57 2010	(r1895)
+++ cpu/arm/boot.fth	Thu Jul 22 09:02:07 2010	(r1896)
@@ -54,14 +54,9 @@
    str     r1,'user dp         	       \ set here
 
    str     r8,'user memtop
-   sub     sp,r8,#0x40
+   sub     sp,r8,#0x40                 \ Guard band
    \ Now the stacks are just below the end of our memory
 
-   ps-size-t rs-size-t + #
-   sub     r8,r8,*
-   sub     r8,r8,r12                        
-   str     r8,'user limit
-
    str     r7,'user syscall-vec
    str     r10,'user #args
    str     r11,'user args
@@ -77,7 +72,16 @@
    dec     sp,*
    dec     sp,#0x20              
    str     sp,'user sp0
+
+   mov     r8,sp
+
+   ps-size-t #
+   dec     r8,*
+   sub     r8,r8,r12            \ Heap size
+   str     r8,'user limit       \ Initial heap will be from limit to bottom of stack
+
    inc     sp,1cell             \ account for the top of stack register
+
    adr     ip,'body cold
 c;
 

Modified: cpu/arm/mmp2/addrs.fth
==============================================================================
--- cpu/arm/mmp2/addrs.fth	Thu Jul 22 08:54:57 2010	(r1895)
+++ cpu/arm/mmp2/addrs.fth	Thu Jul 22 09:02:07 2010	(r1896)
@@ -2,7 +2,7 @@
 h# 2000.0000 constant total-ram-size
 
 h# 1fc0.0000 constant fb-pa
-h#   40.0000 constant fb-size
+h#   20.0000 constant fb-size  \ The screen use a little more than 1 MiB at 800x480x24
 
 fb-pa constant available-ram-size
 
@@ -11,7 +11,7 @@
 ' (memory?) to memory?
 
 \ OFW implementation choices
-h# 0040.0000 constant fw-pa
+h# 1fe0.0000 constant fw-pa
 
 [ifdef] virtual-mode
 h# f700.0000 constant fw-virt-base
@@ -21,17 +21,13 @@
 0 value fw-virt-size
 [then]
 
-h# 0010.0000 constant /fw-ram
+h# 0020.0000 constant /fw-ram
 
 h# 0110.0000 constant def-load-base
 
 \ The heap starts at RAMtop, which on this system is "fw-pa /fw-ram +"
 
-\ We leave some memory in the /memory available list above the heap
-\ for DMA allocation by the sound and USB driver.  OFW's normal memory
-\ usage thus fits in one 4M page-directory mapping region.
-
-h#  18.0000 constant heap-size
+h#  10.0000 constant heap-size
 heap-size constant initial-heap-size
 
 h# 4000 constant page-table-pa

Modified: cpu/arm/mmp2/boot.fth
==============================================================================
--- cpu/arm/mmp2/boot.fth	Thu Jul 22 08:54:57 2010	(r1895)
+++ cpu/arm/mmp2/boot.fth	Thu Jul 22 09:02:07 2010	(r1896)
@@ -8,15 +8,19 @@
    \ Put the arguments in safe registers
    sub   r6,lr,#0x8c        \ r6 points to header (lr set by code at origin)
    mov   r7,#0              \ r7: functions
-   add   r8,r6,0x200000     \ r8: memtop - 2MiB above load address
+   add   r8,r6,`/fw-ram`    \ r8: memtop - 2MiB above load address
                             \ r9 is up
    mov   r10,#0             \ r10: argc
    mov   r11,r2             \ r11: argv (kernel args)
    mov   r12,`initial-heap-size`  \ r12: initial-heap-size
-   mov   r3,#0
+
+   \ Debug - snapshot some register values
+   mov   r3,#0x100
    str   r0,[r3],#4
    str   r1,[r3],#4
    str   r2,[r3],#4
+   str   r8,[r3],#4
+   str   r6,[r3],#4
 
    b     'code start-forth  \ Branch to the generic startup code
 end-code

Added: cpu/arm/mmp2/build/Linux-debug.txt
==============================================================================
--- /dev/null	00:00:00 1970	(empty, because file is newly added)
+++ cpu/arm/mmp2/build/Linux-debug.txt	Thu Jul 22 09:02:07 2010	(r1896)
@@ -0,0 +1,32 @@
+\ This is a recipe for using OFW to debug into the Linux kernel
+\ startup.  You can cut/paste groups into the serial window
+
+fatload mmc 1:1 0x1f800000 ofw.rom ; boot 0x1f800000
+fatload mmc 1:1 0x1fe00000 ofw.rom ; boot 0x1fe00000
+ 
+dev /memory 1f800000 400000 0 claim
+load ext:\zimage
+
+1100134 till  \ After uncompress
+--bp
+
+208064 till   \ About to turn on MMU
+--bp 
+
+text-off  ofw-sections      \ Put OFW in pdir
+vector-base f.0000 80 move  \ Clone vector table to xxxf.0000
+c0e page-table@ fff la+ l!  \ Alias vector table at ffff.0000
+step                        \ Turn on MMU, high vector loc
+
+c0009fb0 till  \ paging_init
+--bp
+
+e35e041f c000b6e8 instruction!  \ Stop clearing PDIR at Forth loc - Changes MODULES_VADDR
+c000b6f0 till                   \ Just before second pmd_clear loop
+--bp
+2000.0000 to r14                \ Bump addr to skip OFW mapping
+
+e35104d4 c000b76c instruction!  \ Change VMALLOC_END to device physical base to preserve device access
+
+\ Now can set breakpoints at other places
+c0010130 till  \ memzero

Modified: cpu/arm/mmp2/build/Makefile
==============================================================================
--- cpu/arm/mmp2/build/Makefile	Thu Jul 22 08:54:57 2010	(r1895)
+++ cpu/arm/mmp2/build/Makefile	Thu Jul 22 09:02:07 2010	(r1896)
@@ -5,14 +5,14 @@
 CLIENTDIR=../../../../clients
 CLIENTPROGS=
 
-all: mmp2.rom tags
+all: ofw.rom tags
 
-mmp2.tag: mmp2.rom
+ofw.tag: ofw.rom
 
-tags: mmp2.tag
+tags: ofw.tag
 	@${BASEDIR}/forth/lib/toctags ${BASEDIR} ${TAGFILES}
 
-mmp2.rom: FORCE build ${CLIENTPROGS}
+ofw.rom: FORCE build ${CLIENTPROGS}
 	./build $@
 
 ../../${OS}/forth:

Modified: cpu/arm/mmp2/devices.fth
==============================================================================
--- cpu/arm/mmp2/devices.fth	Thu Jul 22 08:54:57 2010	(r1895)
+++ cpu/arm/mmp2/devices.fth	Thu Jul 22 09:02:07 2010	(r1896)
@@ -62,7 +62,7 @@
 ' com1 is fallback-device   
 
 0 0  " d420b000"  " /" begin-package
-   " screen" name
+   " display" name
    fload ${BP}/cpu/arm/mmp2/lcdcfg.fth
    fload ${BP}/cpu/arm/mmp2/dsi.fth
 
@@ -94,7 +94,7 @@
    ' display-remove   is-remove
    ' display-selftest is-selftest
 end-package
-devalias screen /screen
+devalias screen /display
    
 devalias keyboard /keyboard
 

Modified: cpu/arm/mmp2/fw.bth
==============================================================================
--- cpu/arm/mmp2/fw.bth	Thu Jul 22 08:54:57 2010	(r1895)
+++ cpu/arm/mmp2/fw.bth	Thu Jul 22 09:02:07 2010	(r1896)
@@ -152,7 +152,8 @@
 [ifdef] virtual-mode
 : (initial-heap)  ( -- adr len )  sp0 @ ps-size -  dict-limit  tuck -  ;
 [else]
-: (initial-heap)  ( -- adr len )  RAMtop heap-size  ;
+   \ : (initial-heap)  ( -- adr len )  RAMtop heap-size  ;
+: (initial-heap)  ( -- adr len )  limit heap-size  ;
 [then]
 ' (initial-heap) is initial-heap
 headers
@@ -188,6 +189,7 @@
 devalias nfs net//obp-tftp:last//nfs
 
 fload ${BP}/cpu/arm/linux.fth
+h# 20.0000 to linux-params  \ The Jasper Linux kernel fails unless the params are between 0x20.0000 and 0x20.4000
 d# 2382 to arm-linux-machine-type  \ Marvell Jasper
 
 \ Add a tag describing the linear frame buffer

Modified: cpu/arm/mmp2/mmuon.fth
==============================================================================
--- cpu/arm/mmp2/mmuon.fth	Thu Jul 22 08:54:57 2010	(r1895)
+++ cpu/arm/mmp2/mmuon.fth	Thu Jul 22 09:02:07 2010	(r1896)
@@ -11,7 +11,7 @@
 
 
 : map-section  ( pa+mode va -- )
-   d# 18 rshift  page-table@ +  l!
+   d# 18 rshift  page-table@ +  tuck l!  clean-d$-entry
 ;
 : map-sections  ( pa mode va size -- )
    2>r  +  2 or   2r>     ( pa+mode va size )
@@ -22,13 +22,18 @@
    drop
 ;
 
+: ofw-sections  ( -- )
+   h# 0000.0000  h# c0e  over  fb-pa        map-sections  \ Cache and write bufferable
+   fw-pa         h# c0e  over  /fw-ram      map-sections  \ Cache and write bufferable
+   fb-pa         h# c06  over  fb-size      map-sections  \ Write bufferable
+   h# d400.0000  h# c02  over  h# 0040.0000 map-sections  \ I/O - no caching or buffering
+;
+
 : setup-sections
    page-table-pa page-table!
    page-table-pa /page-table erase
 
-   h# 0000.0000 h# c0e             0 fb-pa        map-sections  \ Cache and write bufferable
-   fb-pa        h# c06  fb-pa        fb-size      map-sections  \ Write bufferable
-   h# d400.0000 h# c02  h# d400.0000 h# 0100.0000 map-sections  \ I/O - no caching or buffering
+   ofw-sections
 ;
 \ Do we need to map SRAM and DDRC ?
 

Modified: cpu/arm/scc.fth
==============================================================================
--- cpu/arm/scc.fth	Thu Jul 22 08:54:57 2010	(r1895)
+++ cpu/arm/scc.fth	Thu Jul 22 09:02:07 2010	(r1896)
@@ -3,27 +3,84 @@
 
 hex
 code scc-id@            ( -- n )   psh tos,sp  mrc p15,0,tos,cr0,cr0,0  c;
+code cache-type@        ( -- n )   psh tos,sp  mrc p15,0,tos,cr0,cr0,1  c;
+code tlb-type@          ( -- n )   psh tos,sp  mrc p15,0,tos,cr0,cr0,3  c;
 code control@           ( -- n )   psh tos,sp  mrc p15,0,tos,cr1,cr0,0  c;
 code ttbase@            ( -- n )   psh tos,sp  mrc p15,0,tos,cr2,cr0,0  c;
+code ttbase0@           ( -- n )   psh tos,sp  mrc p15,0,tos,cr2,cr0,0  c;
+code ttbase1@           ( -- n )   psh tos,sp  mrc p15,0,tos,cr2,cr1,0  c;
+code ttcontrol@         ( -- n )   psh tos,sp  mrc p15,0,tos,cr2,cr2,0  c;
 code domain-access@     ( -- n )   psh tos,sp  mrc p15,0,tos,cr3,cr0,0  c;
 code fault-status@      ( -- n )   psh tos,sp  mrc p15,0,tos,cr5,cr0,0  c;
+code i-fault-status@    ( -- n )   psh tos,sp  mrc p15,0,tos,cr5,cr1,0  c;
 code fault-address@     ( -- n )   psh tos,sp  mrc p15,0,tos,cr6,cr0,0  c;
+code wp-fault-address@  ( -- n )   psh tos,sp  mrc p15,0,tos,cr6,cr1,0  c;
+code i-fault-address@   ( -- n )   psh tos,sp  mrc p15,0,tos,cr6,cr2,0  c;
 
 code control!           ( n -- )   mcr p15,0,tos,cr1,cr0,0  pop tos,sp  c;
 code ttbase!            ( n -- )   mcr p15,0,tos,cr2,cr0,0  pop tos,sp  c;
+code ttbase0!           ( n -- )   mcr p15,0,tos,cr2,cr0,0  pop tos,sp  c;
+code ttbase1!           ( n -- )   mcr p15,0,tos,cr2,cr1,0  pop tos,sp  c;
+code ttcontrol!         ( n -- )   mcr p15,0,tos,cr2,cr2,0  pop tos,sp  c;
 code domain-access!     ( n -- )   mcr p15,0,tos,cr3,cr0,0  pop tos,sp  c;
 code fault-status!      ( n -- )   mcr p15,0,tos,cr5,cr0,0  pop tos,sp  c;
+code i-fault-status!    ( n -- )   mcr p15,0,tos,cr5,cr1,0  pop tos,sp  c;
 code fault-address!     ( n -- )   mcr p15,0,tos,cr6,cr0,0  pop tos,sp  c;
-code flush-i&d$         ( -- )     mcr p15,0,r0,cr7,cr7,0  c;
+code wp-fault-address!  ( n -- )   mcr p15,0,tos,cr6,cr1,0  pop tos,sp  c;
+code i-fault-address!   ( n -- )   mcr p15,0,tos,cr6,cr2,0  pop tos,sp  c;
+
+code c7-wfi             ( -- )     mcr p15,0,r0,cr7,cr0,4  c;
+
 code flush-i$           ( -- )     mcr p15,0,r0,cr7,cr5,0  c;
+code flush-i$-entry     ( va -- )  mcr p15,0,tos,cr7,cr5,1  pop tos,sp c;
+code flush-i$-entry-way ( sw -- )  mcr p15,0,tos,cr7,cr5,2  pop tos,sp c;
+code flush-prefetch     ( -- )     mcr p15,0,r0,cr7,cr5,4  c;
+code flush-bt$          ( -- )     mcr p15,0,r0,cr7,cr5,6  c;
+code flush-bt$-entry    ( va -- )  mcr p15,0,tos,cr7,cr5,7  pop tos,sp c;
+
 code flush-d$           ( -- )     mcr p15,0,r0,cr7,cr6,0  c;
-code flush-d$-entry     ( va -- )  mcr p15,0,tos,cr7,cr6,1   pop tos,sp  c;
+code flush-d$-entry     ( va -- )  mcr p15,0,tos,cr7,cr6,1  pop tos,sp  c;
+code flush-d$-entry-way ( sw -- )  mcr p15,0,tos,cr7,cr6,2  pop tos,sp  c;
+
+code flush-i&d$         ( -- )     mcr p15,0,r0,cr7,cr7,0  c;
+code flush-u$           ( -- )     mcr p15,0,r0,cr7,cr7,0  c;
+code flush-u$-entry     ( va -- )  mcr p15,0,tos,cr7,cr7,1  pop tos,sp  c;
+code flush-u$-way       ( sw -- )  mcr p15,0,tos,cr7,cr7,2  pop tos,sp  c;
+
+code clean-d$           ( -- )     mcr p15,0,r0,cr7,cr10,0  c;
 code clean-d$-entry     ( va -- )  mcr p15,0,tos,cr7,cr10,1  pop tos,sp  c;
+code clean-d$-way       ( sw -- )  mcr p15,0,tos,cr7,cr10,2  pop tos,sp  c;
+code test&clean-d$      ( -- )     mcr p15,0,r0,cr7,cr10,3  c;
+
+code clean-u$           ( -- )     mcr p15,0,r0,cr7,cr11,0  c;
+code clean-u$-entry     ( va -- )  mcr p15,0,tos,cr7,cr11,1  pop tos,sp  c;
+code clean-u$-way       ( sw -- )  mcr p15,0,tos,cr7,cr11,2  pop tos,sp  c;
+
+code clean&flush-d$             ( -- )     mcr p15,0,r0,cr7,cr14,0  c;
+code clean&flush-d$-entry       ( va -- )  mcr p15,0,tos,cr7,cr14,1  pop tos,sp  c;
+code clean&flush-d$-entry-way   ( sw -- )  mcr p15,0,tos,cr7,cr14,2  pop tos,sp  c;
+code test,clean&flush-d$        ( -- )     mcr p15,0,tos,cr7,cr14,3  c;
+
+code clean&flush-u$             ( -- )     mcr p15,0,r0,cr7,cr15,0  c;
+code clean&flush-u$-entry       ( va -- )  mcr p15,0,tos,cr7,cr15,1  pop tos,sp  c;
+code clean&flush-u$-entry-way   ( sw -- )  mcr p15,0,tos,cr7,cr15,2  pop tos,sp  c;
+
+
+
 code drain-write-buffer ( -- )     mcr p15,0,r0,cr7,cr10,4  c;
+alias data-sync-barrier drain-write-buffer
+code drain-write-buffer ( -- )     mcr p15,0,r0,cr7,cr10,4  c;
+code data-memory-barrier ( -- )    mcr p15,0,r0,cr7,cr10,5  c;
+
 code flush-i&d-tlb      ( -- )     mcr p15,0,r0,cr8,cr7,0  c;
+code flush-i&d-tlb-entry ( va -- ) mcr p15,0,tos,cr8,cr7,1  pop tos,sp  c;
+code flush-i&d-tlb-asid  ( as -- ) mcr p15,0,tos,cr8,cr7,2  pop tos,sp  c;
 code flush-i-tlb        ( -- )     mcr p15,0,r0,cr8,cr5,0  c;
+code flush-i-tlb-entry  ( va -- )  mcr p15,0,tos,cr8,cr5,1  pop tos,sp  c;
+code flush-i-tlb-asid   ( as -- )  mcr p15,0,tos,cr8,cr5,2  pop tos,sp  c;
 code flush-d-tlb        ( -- )     mcr p15,0,r0,cr8,cr6,0  c;
 code flush-d-tlb-entry  ( va -- )  mcr p15,0,tos,cr8,cr6,1  pop tos,sp  c;
+code flush-d-tlb-asid   ( as -- )  mcr p15,0,tos,cr8,cr6,1  pop tos,sp  c;
 
 code enable-odd-lfsr    ( -- )     mcr p15,0,r0,cr15,cr1,1  c;
 code enable-even-lfsr   ( -- )     mcr p15,0,r0,cr15,cr2,1  c;
@@ -53,6 +110,23 @@
    /cache-line +loop
 ;
 
+code turn-off-dcache  ( adr len -- )
+   pop r0,sp  \ tos:len r0:adr
+   cmp tos,#0
+   <>  if
+      begin
+         mcr   p15,0,r0,cr7,cr10,1    \ Clean D$ entry
+         mcr   p15,0,r0,cr7,cr6,1     \ Flush D$ entry
+         add   r0,r0,#32              \ Advance to next line
+         decs  tos,#32     \ Assume cache line size of 32 bytes
+      0= until
+   then
+   mcr  p15,0,r0,cr7,cr10,4           \ Drain write buffer
+   mrc  p15,0,r0,cr1,cr0,0            \ Read control register
+   bic  r0,r0,#4                      \ Clear DCache enable bit
+   mcr  p15,0,r0,cr1,cr0,0            \ Write control register
+c;
+
 \ System-dependent function to flush the entire cache
 \ (In normal ARM nomenclature, as used by most of the words in this file,
 \ "flush" means "invalidate without ensuring that cached data has been

Modified: cpu/arm/target.fth
==============================================================================
--- cpu/arm/target.fth	Thu Jul 22 08:54:57 2010	(r1895)
+++ cpu/arm/target.fth	Thu Jul 22 09:02:07 2010	(r1896)
@@ -36,9 +36,9 @@
       /l-t constant /token-t
       /l-t constant /link-t
 /token-t   constant /defer-t
-/n-t 800 * constant user-size-t
-/n-t 100 * constant ps-size-t
-/n-t 100 * constant rs-size-t
+/n-t th c00 * constant user-size-t
+/n-t th 200 * constant ps-size-t
+/n-t th 200 * constant rs-size-t
 /l-t constant /user#-t
 
 \ 32 bit host Forth compiling 32-bit target Forth



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