[openfirmware] [commit] r2517 - in cpu/arm: mmp2 olpc/1.75
repository service
svn at openfirmware.info
Fri Sep 16 02:47:50 CEST 2011
Author: wmb
Date: Fri Sep 16 02:47:50 2011
New Revision: 2517
URL: http://tracker.coreboot.org/trac/openfirmware/changeset/2517
Log:
OLPC XO-1.75 - Checkpoint of suspend code - seems to be working for the most part.
Modified:
cpu/arm/mmp2/dramrecal.fth
cpu/arm/mmp2/rtc.fth
cpu/arm/olpc/1.75/prefw.bth
Modified: cpu/arm/mmp2/dramrecal.fth
==============================================================================
--- cpu/arm/mmp2/dramrecal.fth Fri Sep 16 02:46:57 2011 (r2516)
+++ cpu/arm/mmp2/dramrecal.fth Fri Sep 16 02:47:50 2011 (r2517)
@@ -97,11 +97,7 @@
mov r1, #0x80000000 \ PHY_SYNC_EN
str r1, [r0, #0x240] \ PHY_CTRL14
- ldr r1, [r0, #0x230] \ PHY_CTRL13
- orr r1,r1,#0xf0000000 \ DLL_RESET_TIMER: 15*256 memory clocks
-\ mov r1, #0xf0000000 \ DLL_RESET_TIMER: 15*256 memory clocks
-\ orr r1, r1, #0x0040 \ DLL_PHSEL: 4 (45 + 4*3 = 57 degrees) - adjust?
- str r1, [r0, #0x230] \ PHY_CTRL13
+ \ There used to be code to set register 230, but Marvell says it is unnecessary.
mov r1, #0x20000000 \ PHY_DLL_RESET
str r1, [r0, #0x240] \ PHY_CTRL14
@@ -172,15 +168,6 @@
mov sp,r7
c;
-: +apbc ( offset -- io-offset ) h# 01.5000 + ;
-: +apmu ( offset -- io-offset ) h# 28.2800 + ;
-: +mpmu ( offset -- io-offset ) h# 05.0000 + ;
-: +scu ( offset -- io-offset ) h# 28.2c00 + ;
-: +icu ( offset -- io-offset ) h# 28.2000 + ;
-
-: io-set ( mask offset -- ) dup io@ rot or swap io! ;
-: io-clr ( mask offset -- ) dup io@ rot invert and swap io! ;
-
: apbc-clr-rst ( offset -- ) +apbc 4 swap io-clr ;
: apbc-set-rst ( offset -- ) +apbc 4 swap io-set ;
@@ -217,40 +204,40 @@
h# f0 h# 1c +scu io-clr \ SCU_MCB_CONF
;
: disable-apmu-clks ( -- )
- h# 1b h# 54 +apmu io-clr \ PMUA_SDH0_CLK_RES_CTRL
- h# 1b h# 58 +apmu io-clr \ PMUA_SDH1_CLK_RES_CTRL
- h# 1b h# e8 +apmu io-clr \ PMUA_SDH2_CLK_RES_CTRL
- h# 1b h# d4 +apmu io-clr \ PMUA_SMC_CLK_RES_CTRL
- h# 3f h# 60 +apmu io-clr \ PMUA_NF_CLK_RES_CTRL
- h# 3f h# d8 +apmu io-clr \ PMUA_MSPRO_CLK_RES_CTRL - XO does not use MSPRO
- h# 12 h# 10c +apmu io-clr \ PMUA_AUDIO_CLK_RES_CTRL
- h# 1fffd h# dc +apmu io-clr \ PMUA_GLB_CLK_RES_CTRL
-\ 0 h# 68 +apmu io! \ PMUA_WTM_CLK_RES_CTRL
- h# 9 h# 5c +apmu io-clr \ PMUA_USB_CLK_RES_CTRL
+ h# 1b h# 54 +pmua io-clr \ PMUA_SDH0_CLK_RES_CTRL
+ h# 1b h# 58 +pmua io-clr \ PMUA_SDH1_CLK_RES_CTRL
+ h# 1b h# e8 +pmua io-clr \ PMUA_SDH2_CLK_RES_CTRL
+ h# 1b h# d4 +pmua io-clr \ PMUA_SMC_CLK_RES_CTRL
+ h# 3f h# 60 +pmua io-clr \ PMUA_NF_CLK_RES_CTRL
+ h# 3f h# d8 +pmua io-clr \ PMUA_MSPRO_CLK_RES_CTRL - XO does not use MSPRO
+ h# 12 h# 10c +pmua io-clr \ PMUA_AUDIO_CLK_RES_CTRL
+ h# 1fffd h# dc +pmua io-clr \ PMUA_GLB_CLK_RES_CTRL
+\ 0 h# 68 pmua! \ PMUA_WTM_CLK_RES_CTRL
+ h# 9 h# 5c +pmua io-clr \ PMUA_USB_CLK_RES_CTRL
;
: enable-apmu-clks ( -- )
- h# 1b h# 54 +apmu io-set \ PMUA_SDH0_CLK_RES_CTRL
- h# 1b h# 58 +apmu io-set \ PMUA_SDH1_CLK_RES_CTRL
- h# 1b h# e8 +apmu io-set \ PMUA_SDH2_CLK_RES_CTRL
- h# 1b h# d4 +apmu io-set \ PMUA_SMC_CLK_RES_CTRL \ ??? what is this and why is it on?
- h# 3f h# 60 +apmu io-set \ PMUA_NF_CLK_RES_CTRL \ Should this be on?
-\ h# 3f h# d8 +apmu io-set \ PMUA_MSPRO_CLK_RES_CTRL
- h# 12 h# 10c +apmu io-set \ PMUA_AUDIO_CLK_RES_CTRL
- h# 1fffd h# dc +apmu io-set \ PMUA_GLB_CLK_RES_CTRL
-\ h# 1b h# 68 +apmu io! \ PMUA_WTM_CLK_RES_CTRL
- h# 9 h# 5c +apmu io-set \ PMUA_USB_CLK_RES_CTRL
+ h# 1b h# 54 +pmua io-set \ PMUA_SDH0_CLK_RES_CTRL
+ h# 1b h# 58 +pmua io-set \ PMUA_SDH1_CLK_RES_CTRL
+ h# 1b h# e8 +pmua io-set \ PMUA_SDH2_CLK_RES_CTRL
+ h# 1b h# d4 +pmua io-set \ PMUA_SMC_CLK_RES_CTRL \ ??? what is this and why is it on?
+ h# 3f h# 60 +pmua io-set \ PMUA_NF_CLK_RES_CTRL \ Should this be on?
+\ h# 3f h# d8 +pmua io-set \ PMUA_MSPRO_CLK_RES_CTRL
+ h# 12 h# 10c +pmua io-set \ PMUA_AUDIO_CLK_RES_CTRL
+ h# 1fffd h# dc +pmua io-set \ PMUA_GLB_CLK_RES_CTRL
+\ h# 1b h# 68 pmua! \ PMUA_WTM_CLK_RES_CTRL
+ h# 9 h# 5c +pmua io-set \ PMUA_USB_CLK_RES_CTRL
;
: disable-mpmu-clks ( -- )
- h# a010 h# 1024 +mpmu io! \ MPMU_ACGR
+ h# a010 h# 1024 mpmu! \ MPMU_ACGR
- h# a010 h# 0024 +mpmu io! \ MPMU_CGR_SP ???
+ h# a010 h# 0024 mpmu! \ MPMU_CGR_SP ???
\ h# 2000.0000 h# 414 +mpmu io-clr \ MPMU_PLL2_CTRL1
h# 8000.0000 h# 0040 +mpmu io-clr \ MPMU_ISCCR1
h# 8000.0000 h# 0044 +mpmu io-clr \ MPMU_ISCCR2
;
: enable-mpmu-clks ( -- )
- h# dffe.fffe h# 1024 +mpmu io! \ MPMU_ACGR
+ h# dffe.fffe h# 1024 mpmu! \ MPMU_ACGR
\ h# 2000.0000 h# 0414 +mpmu io-set \ MPMU_PLL2_CTRL1
h# 8000.0000 h# 0040 +mpmu io-set \ MPMU_ISCCR1
h# 8000.0000 h# 0044 +mpmu io-set \ MPMU_ISCCR2
@@ -309,8 +296,8 @@
\ WAKEUP7: PMIC INT
5 value sleep-depth
: setup-wakeup-sources ( -- mask )
- h# 0002.0094 h# 4c +mpmu io! \ RTC_ALARM, WAKEUP7, WAKEUP4, WAKEUP2
-\ h# 0002.0094 h# 104c +mpmu io! \ RTC_ALARM, WAKEUP7, WAKEUP4, WAKEUP2 ???
+ h# 0002.0094 h# 4c mpmu! \ RTC_ALARM, WAKEUP7, WAKEUP4, WAKEUP2
+\ h# 0002.0094 h# 104c mpmu! \ RTC_ALARM, WAKEUP7, WAKEUP4, WAKEUP2 ???
h# ff08.7fff ( mask ) \ Enable all wakeup ports
;
: block-irqs ( -- ) 1 h# 110 +icu io! ;
@@ -319,8 +306,8 @@
0 value save-idlecfg
: restore-run-state ( -- )
- save-apcr h# 1000 +mpmu io! ( ) \ Restore APCR
- save-idlecfg h# 18 +apmu io! ( ) \ Restore IDLE_CFG
+ save-apcr h# 1000 mpmu! ( ) \ Restore APCR
+ save-idlecfg h# 18 pmua! ( ) \ Restore IDLE_CFG
;
\ Questions:
\ Meaning of various connect type options
@@ -340,21 +327,25 @@
\ Security processor setup
sleep-depth 4 >= if \ state at least POWER_MODE_CHIP_SLEEP (turn off most of SoC)
- h# fe08.6000 0 +mpmu io! \ In SP, set AXISD, resvd, SLPEN, SPSD, DDRCORSD, APBSD resvd, VCXOSD
+\ h# fe08.6000 0 mpmu! \ In SP, set AXISD, resvd, SLPEN, SPSD, DDRCORSD, APBSD resvd, VCXOSD
+ \ We keep PMUM_BBDP (bit 25) off because that saves 60 mW
+ h# fc08.6000 0 mpmu! \ In SP, set AXISD, resvd, SLPEN, SPSD, DDRCORSD, APBSD resvd, VCXOSD
then
sleep-depth 3 = if \ state at least POWER_MODE_APPS_SLEEP (turn off slow IO)
- h# de00.6000 0 +mpmu io! \ In SP, set AXISD, resvd, SPSD, DDRCORSD, APBSD resvd,
+\ h# de00.6000 0 mpmu! \ In SP, set AXISD, resvd, SPSD, DDRCORSD, APBSD resvd,
+ \ We keep PMUM_BBDP (bit 25) off because that saves 60 mW
+ h# dc00.6000 0 mpmu! \ In SP, set AXISD, resvd, SPSD, DDRCORSD, APBSD resvd,
then
\ Linux value
-\ h# 8030.0020 h# 14 +apmu io! \ IN PMUA_SP_IDLE_CFG, set , DIVIDER_RESET_EN, SP_DIS_MC_SW_REQ, SP_MC_WAKE_EN, TCM_STATE_RETAIN
- h# 8020.0020 h# 14 +apmu io! \ IN PMUA_SP_IDLE_CFG, set , DIVIDER_RESET_EN, SP_DIS_MC_SW_REQ, TCM_STATE_RETAIN
+\ h# 8030.0020 h# 14 pmua! \ IN PMUA_SP_IDLE_CFG, set , DIVIDER_RESET_EN, SP_DIS_MC_SW_REQ, SP_MC_WAKE_EN, TCM_STATE_RETAIN
+ h# 8020.0020 h# 14 pmua! \ IN PMUA_SP_IDLE_CFG, set , DIVIDER_RESET_EN, SP_DIS_MC_SW_REQ, TCM_STATE_RETAIN
\ PJ4 setup
- h# 1000 +mpmu io@ to save-apcr
- h# 18 +apmu io@ to save-idlecfg
+ h# 1000 mpmu@ to save-apcr
+ h# 18 pmua@ to save-idlecfg
save-apcr ( apcr )
h# ac08.0000 invert and ( apcr' ) \ Clear AXISD, SLPEN, DDRCORSD, APBSD, VCXOSD
@@ -393,36 +384,69 @@
h# 0020.0000 or ( apcr idle' ) \ PJ_DIS_MC_SW_REQ - disable idle entry using software register bits
h# 0010.0000 or ( apcr idle' ) \ PJ_MC_WAKE_EN - wake memory controller when core wakes
- 0 h# b0 +apmu io! ( apcr idle ) \ PMUA_MC_HW_SLP_TYPE - self-refresh power down
+ 0 h# b0 pmua! ( apcr idle ) \ PMUA_MC_HW_SLP_TYPE - self-refresh power down
- h# 18 +apmu io! ( apcr ) \ Set IDLE_CFG register
- h# 1000 +mpmu io! ( ) \ Set APCR register
+ h# 18 pmua! ( apcr ) \ Set IDLE_CFG register
+ h# 1000 mpmu! ( ) \ Set APCR register
\ end mmp2_pm_enter_lowpower_mode(state)
;
-: screen-dark
- " screen-ih iselect h# 12 mode! 0 h# 190 lcd! iunselect" eval \ Saves 1.05W
- 0 h# 4c +apmu io! \ Kill the display clocks - saves 100 mW
- \ 0 h# 54 +apmu io! \ Kill the SDIO 0 clocks - insignificant savings
- \ 0 h# 58 +apmu io! \ Kill the SDIO 1 clocks - insignificant savings
- d# 34 gpio-clr \ Kill the WLAN power - saves 100 mW
+: keyboard-power-on ( -- ) d# 148 gpio-clr ;
+: keyboard-power-off ( -- ) d# 148 gpio-set ;
+: wlan-power-on ( -- ) d# 34 gpio-set ;
+: wlan-power-off ( -- ) d# 34 gpio-clr ;
+: dcon-power-on ( -- ) 1 h# 26 ec-cmd-b! ;
+: dcon-power-off ( -- ) 0 h# 26 ec-cmd-b! ;
+h# ffff value sleep-mask
+: screen-off
+ sleep-mask 1 and if h# 12 " mode!" $call-screen then \ DCON power down
+ 0 h# 190 " lcd!" $call-screen
+ 0 h# 4c pmua! \ Kill the display clocks - saves 100 mW
+ \ 0 h# 54 pmua! \ Kill the SDIO 0 clocks - insignificant savings
+ \ 0 h# 58 pmua! \ Kill the SDIO 1 clocks - insignificant savings
+ sleep-mask 2 and if dcon-power-off then \ saves 80 mW
+ sleep-mask 4 and if keyboard-power-off then \ Should save about 17 mW
+ sleep-mask 8 and if wlan-power-off then \ saves 100 mW
+;
+: screen-on ( -- )
+ sleep-mask 8 and if wlan-power-on then
+ sleep-mask 4 and if keyboard-power-on then
+ sleep-mask 2 and if dcon-power-on d# 50 ms then \ saves 80 mW
+ h# 71b h# 4c pmua!
+ h# 8001100 h# 190 " lcd!" $call-screen
+ sleep-mask 1 and if h# 69 " mode!" $call-screen then \ DCON power up
;
+
: stdin-idle-on ['] safe-idle to stdin-idle d# 15 enable-interrupt ;
-: stdin-idle-off ['] noop to stdin-idle install-uart-io d# 15 disable-interrupt ;
+: stdin-idle-off ['] noop to stdin-idle ( install-uart-io ) d# 15 disable-interrupt ;
: timers-off ( -- )
0 h# 14048 io! \ Disable interrupts from the tick timer
7 h# 1407c io! \ Clear any pending interrupts
h# f disable-interrupt \ Block timer interrupt
;
+: timers-on ( -- )
+ 1 h# 14048 io! \ Enable interrupts from the tick timer
+ 7 h# 1407c io! \ Clear any pending interrupts
+ h# f enable-interrupt \ Unblock timer interrupt
+ reschedule-tick
+;
+
+: power-islands-off ( -- )
+ 0 h# 10c pmua! \ Turn off audio power island
+;
+: power-islands-on ( -- )
+ h# 712 h# 10c pmua! \ Turn on audio power island
+;
: str ( -- )
+ disable-interrupts
timers-off
- screen-dark
+ screen-off
stdin-idle-off
- 5 h# 38 +mpmu io! \ Use 32 kHz clock instead of VCXO for slow clock
+ 5 h# 38 mpmu! \ Use 32 kHz clock instead of VCXO for slow clock
\ OLPC: Unmask main PMU interrupt - don't know if this is necessary
\ h# 400 h# 174 +icu io-clr
@@ -435,13 +459,13 @@
setup-sleep-state
- h# 000c.0000 h# 8c +apmu io-set \ Power down CoreSight SRAM
+ h# 000c.0000 h# 8c +pmua io-set \ Power down CoreSight SRAM
\ TODO - need to power down sram/l2$
\ mmp2_cpu_disable_l2(0);
\ outer_cache.flush_range(0, -1ul);
- \ TODO - handle low power island?
+ power-islands-off
disable-clks
@@ -454,11 +478,15 @@
enable-clks
- ." STR out" cr
+ power-islands-on
+
\ mmp2_cpu_enable_l2(0);
\ idle_cfg &= (~PMUA_MOH_SRAM_PWRDWN);
stdin-idle-on
+ screen-on
+ timers-on
+ enable-interrupts
;
\ LICENSE_BEGIN
Modified: cpu/arm/mmp2/rtc.fth
==============================================================================
--- cpu/arm/mmp2/rtc.fth Fri Sep 16 02:46:57 2011 (r2516)
+++ cpu/arm/mmp2/rtc.fth Fri Sep 16 02:47:50 2011 (r2517)
@@ -10,8 +10,8 @@
: int5-status@ ( -- value ) h# 28.2154 io@ ;
: enable-rtc ( -- ) h# 81 h# 01.5000 io! ;
: enable-rtc-wakeup ( -- )
- h# 5.004c io@ h# 2.0010 or h# 5.004c io!
- h# 5.104c io@ h# 2.0010 or h# 5.104c io!
+ h# 004c mpmu@ h# 2.0010 or h# 004c mpmu!
+ h# 104c mpmu@ h# 2.0010 or h# 104c mpmu!
;
: soc-rtc@ ( offset -- value ) h# 01.0000 + io@ ;
: soc-rtc! ( value offset -- value ) h# 01.0000 + io! ;
Modified: cpu/arm/olpc/1.75/prefw.bth
==============================================================================
--- cpu/arm/olpc/1.75/prefw.bth Fri Sep 16 02:46:57 2011 (r2516)
+++ cpu/arm/olpc/1.75/prefw.bth Fri Sep 16 02:47:50 2011 (r2517)
@@ -168,6 +168,22 @@
: io! ( value offset -- ) +io l! ;
: io@ ( offset -- value ) +io l@ ;
+: +apbc ( offset -- io-offset ) h# 01.5000 + ;
+: +pmua ( offset -- io-offset ) h# 28.2800 + ;
+: +mpmu ( offset -- io-offset ) h# 05.0000 + ;
+: +scu ( offset -- io-offset ) h# 28.2c00 + ;
+: +icu ( offset -- io-offset ) h# 28.2000 + ;
+
+: io-set ( mask offset -- ) dup io@ rot or swap io! ;
+: io-clr ( mask offset -- ) dup io@ rot invert and swap io! ;
+
+
+: mpmu@ ( offset -- l ) +mpmu io@ ;
+: mpmu! ( l offset -- ) +mpmu io! ;
+
+: pmua@ ( offset -- l ) +pmua io@ ;
+: pmua! ( l offset -- ) +pmua io! ;
+
fload ${BP}/cpu/arm/mmp2/hash.fth \ Hashes - SHA1, SHA-256, MD5
fload ${BP}/cpu/x86/pc/olpc/crypto.fth \ Cryptographic image validation
fload ${BP}/cpu/x86/pc/olpc/lzip.fth \ Access zip images from memory
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